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module top(a, x);
reg [3:0] tmp;
input [3:0] a;
output reg [3:0] x;
always @* begin
x = tmp;
tmp = a;
end
endmodule // top
`ifndef SYNTHESIS
/* Generated by Yosys 0.9+2406 (git sha1 000fd08198, clang++ 7.1.0 -fPIC -Os) */
module top_synth(a, x);
input [3:0] a;
wire [3:0] tmp;
output [3:0] x;
assign tmp = a;
assign x = a;
endmodule
module main;
reg [3:0] a;
wire [3:0] x, x_synth;
top top(a, x);
top_synth top_synth(a, x_synth);
initial begin
a = 0;
#10 a = 1;
#10 $display("x: %d\nx_synth: %d", x, x_synth);
$finish;
end
endmodule
`endif
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