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:
vericert
debug/unhashed
dev-michalis
dev/asplos
dev/div
dev/divider
dev/full-nix-build
dev/mac-op
dev/michalis
dev/scheduling
dev/value
exp/inl-cse-const
master
stable
Vericert is a formally verified high-level synthesis tool.
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path:
root
/
src
/
Verilog
/
PrettyPrint.mli
blob: 843feec61de343b2f34877dadf38b73295164e81 (
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)
1
val
prettyprint
:
Extraction
.
VerilogAST
.
verilog
->
string
