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authorYann Herklotz <git@ymhg.org>2019-04-13 12:21:05 +0100
committerYann Herklotz <git@ymhg.org>2019-04-13 12:21:05 +0100
commitb281cee59daa51ba4607229092274dfa2f801806 (patch)
tree5b8b232f593e4c2d14aaa93ea5856231f12f8623
parent79a6b80ada570123e85590d484a72c810d4d8d0c (diff)
downloadverismith-b281cee59daa51ba4607229092274dfa2f801806.tar.gz
verismith-b281cee59daa51ba4607229092274dfa2f801806.zip
Fix tests passing
-rw-r--r--src/VeriFuzz/Verilog/Gen.hs2
-rw-r--r--src/VeriFuzz/Verilog/Mutate.hs2
-rw-r--r--test/Property.hs10
3 files changed, 6 insertions, 8 deletions
diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs
index 8da4d1a..c325f66 100644
--- a/src/VeriFuzz/Verilog/Gen.hs
+++ b/src/VeriFuzz/Verilog/Gen.hs
@@ -54,7 +54,7 @@ toId = Identifier . ("w" <>) . T.pack . show
toPort :: Identifier -> Gen Port
toPort ident = do
- i <- Hog.int $ Hog.linear 0 100
+ i <- Hog.int $ Hog.linear 1 100
return $ wire i ident
sumSize :: [Port] -> Int
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs
index f4330bc..536ebef 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Verilog/Mutate.hs
@@ -107,7 +107,7 @@ allVars m =
-- $setup
-- >>> import VeriFuzz.Verilog.CodeGen
--- >>> let m = (ModDecl (Identifier "m") [Port Wire False 5 (Identifier "y")] [Port Wire False 5 "x"] [] [])
+-- >>> let m = (ModDecl (Identifier "m") [Port Wire False 0 5 (Identifier "y")] [Port Wire False 0 5 "x"] [] [])
-- >>> let main = (ModDecl "main" [] [] [] [])
-- | Add a Module Instantiation using 'ModInst' from the first module passed to
diff --git a/test/Property.hs b/test/Property.hs
index ba961cf..431a155 100644
--- a/test/Property.hs
+++ b/test/Property.hs
@@ -3,7 +3,7 @@ module Property
)
where
-import Data.Either (fromRight, isRight)
+import Data.Either (either, isRight)
import qualified Data.Graph.Inductive as G
import Hedgehog (Gen, (===))
import qualified Hedgehog as Hog
@@ -42,11 +42,9 @@ parserIdempotent' = Hog.property $ do
p sv === (p . p) sv
where
vshow = show . GenVerilog
- p =
- vshow
- . fromRight (error "Failed idempotent test")
- . parse parseModDecl "idempotent_test.v"
- . alexScanTokens
+ p sv = either (\x -> show x <> "\n" <> sv) vshow
+ . parse parseModDecl "idempotent_test.v"
+ $ alexScanTokens sv
parserInput :: TestTree
parserInput = testProperty "parser input" parserInput'