| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Use HashMap for contextfeature/hashmap | Yann Herklotz | 2019-07-29 | 6 | -68/+147 |
| * | Add benchmark | Yann Herklotz | 2019-07-28 | 3 | -4/+4 |
| * | Add some more performance optimisations | Yann Herklotz | 2019-07-27 | 1 | -1/+5 |
| * | Add faster build to travis | Yann Herklotz | 2019-07-27 | 1 | -0/+1 |
| * | Make the nix build more concise | Yann Herklotz | 2019-07-27 | 4 | -96/+13 |
| * | Add a benchmark | Yann Herklotz | 2019-07-27 | 6 | -61/+196 |
| * | Add benchmark | Yann Herklotz | 2019-07-27 | 1 | -0/+7 |
| * | Move the imports to VeriFuzz.hs | Yann Herklotz | 2019-07-26 | 2 | -7/+11 |
| * | Move Gen.hs to Generate.hs | Yann Herklotz | 2019-07-26 | 3 | -4/+4 |
| * | Add non determinism probability to generation | Yann Herklotz | 2019-07-26 | 4 | -25/+64 |
| * | Remove old way of running tests | Yann Herklotz | 2019-07-23 | 1 | -13/+0 |
| * | Add more documentation about the new build | Yann Herklotz | 2019-07-23 | 1 | -14/+39 |
| * | Bump version to 0.3.1.0v0.3.1.0 | Yann Herklotz | 2019-07-23 | 1 | -2/+2 |
| * | [Fix #52] Correctly resize the modules | Yann Herklotz | 2019-07-23 | 1 | -6/+9 |
| * | Add new maintainer email | Yann Herklotz | 2019-07-23 | 36 | -297/+219 |
| * | Add release to nix | Yann Herklotz | 2019-07-23 | 1 | -0/+2 |
| * | Fix nix build and add to travis | Yann Herklotz | 2019-07-23 | 6 | -47/+53 |
| * | Fix the filtering of the local values | Yann Herklotz | 2019-07-23 | 1 | -1/+4 |
| * | Add end of line | Yann Herklotz | 2019-07-23 | 1 | -1/+1 |
| * | Remove stack and format fuzz | Yann Herklotz | 2019-07-23 | 5 | -52/+111 |
| * | Add .env and fix VeriFuzz.hs | Yann Herklotz | 2019-07-21 | 2 | -23/+22 |
| * | Update default.nix | Yann Herklotz | 2019-07-21 | 2 | -5/+7 |
| * | Merge branch 'master' into fix/resize-modports | Yann Herklotz | 2019-07-21 | 62 | -478/+2202 |
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| | * | Add section about configuration file | Yann Herklotz | 2019-07-05 | 2 | -6/+79 |
| | * | Small changes to the documentation | Yann Herklotz | 2019-07-05 | 1 | -17/+14 |
| | * | Add description to data | Yann Herklotz | 2019-06-29 | 1 | -0/+5 |
| | * | Format files | Yann Herklotz | 2019-06-29 | 32 | -289/+416 |
| | * | Fix pedantic warnings | Yann Herklotz | 2019-06-29 | 5 | -10/+21 |
| | * | Add generated constructs | Yann Herklotz | 2019-06-29 | 1 | -6/+16 |
| | * | Add links to presentation and thesis | Yann Herklotz | 2019-06-29 | 1 | -7/+26 |
| | * | Add some more stats | Yann Herklotz | 2019-06-29 | 1 | -0/+3 |
| | * | Add reported bugs | Yann Herklotz | 2019-06-29 | 1 | -8/+12 |
| | * | Add found bugs | Yann Herklotz | 2019-06-29 | 1 | -0/+19 |
| | * | Add back the simulation | Yann Herklotz | 2019-06-29 | 5 | -63/+60 |
| | * | Add part of the simulator implementation | Yann Herklotz | 2019-06-29 | 3 | -5/+104 |
| | * | Add exclude script | Yann Herklotz | 2019-06-06 | 1 | -0/+37 |
| | * | Format all files | Yann Herklotz | 2019-06-05 | 10 | -104/+143 |
| | * | Fix size in output wire | Yann Herklotz | 2019-06-05 | 1 | -2/+3 |
| | * | Add combination option | Yann Herklotz | 2019-06-05 | 3 | -5/+10 |
| | * | Add median and mean sampling | Yann Herklotz | 2019-06-02 | 1 | -10/+39 |
| | * | Remove dead code | Yann Herklotz | 2019-06-02 | 1 | -1/+1 |
| | * | Add selection for soup | Yann Herklotz | 2019-06-02 | 1 | -1/+1 |
| | * | Add XOR to the output | Yann Herklotz | 2019-06-02 | 2 | -2/+3 |
| | * | Add fix to synthesise correctly with Quartus without MAC | Yann Herklotz | 2019-06-02 | 1 | -1/+2 |
| | * | Add check for quicker reduction | Yann Herklotz | 2019-06-02 | 1 | -17/+19 |
| | * | Add extra experiments | Yann Herklotz | 2019-06-02 | 2 | -0/+66 |
| | * | Fix cyclone_v cell declaration | Yann Herklotz | 2019-06-02 | 1 | -46/+12 |
| | * | Add output | Yann Herklotz | 2019-05-30 | 1 | -3/+3 |
| | * | Fix the conversion | Yann Herklotz | 2019-05-30 | 1 | -3/+13 |
| | * | Add conversion script | Yann Herklotz | 2019-05-30 | 4 | -0/+21 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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