Add necessary exports to AST and CodeGen

2 files changed, 2 insertions, 2 deletions

diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs
index 306366c..7a654fd 100644
--- a/src/VeriFuzz/Verilog/AST.hs
+++ b/src/VeriFuzz/Verilog/AST.hs
@@ -492,7 +492,7 @@ newtype Verilog = Verilog { getVerilog :: [ModDecl] }
 data SourceInfo = SourceInfo { _infoTop :: {-# UNPACK #-} !Text
                              , _infoSrc :: !Verilog
                              }
-                  deriving (Eq, Show)
+                  deriving (Eq, Ord, Data, Show)
 
 $(makeLenses ''Expr)
 $(makeLenses ''ConstExpr)
diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs
index a0ec0cc..6ef1959 100644
--- a/src/VeriFuzz/Verilog/CodeGen.hs
+++ b/src/VeriFuzz/Verilog/CodeGen.hs
@@ -17,7 +17,7 @@ This module generates the code from the Verilog AST defined in
 module VeriFuzz.Verilog.CodeGen
     ( -- * Code Generation
       GenVerilog(..)
-    , genSource
+    , Source(..)
     , render
     )
 where