Add XOR to the output

2 files changed, 3 insertions, 2 deletions

diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs
index bc40de5..828224f 100644
--- a/src/VeriFuzz/Verilog/Gen.hs
+++ b/src/VeriFuzz/Verilog/Gen.hs
@@ -464,7 +464,7 @@ moduleDef top = do
                 ^.. traverse
                 .   portSize
     let clock = Port Wire False 1 "clk"
-    let yport = Port Wire False size "y"
+    let yport = Port Wire False 1 "y"
     let comb  = combineAssigns_ yport local
     return
         . declareMod local
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs
index 66f3c37..8af0182 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Verilog/Mutate.hs
@@ -377,13 +377,14 @@ removeId i = transform trans
 
 combineAssigns :: Port -> [ModItem] -> [ModItem]
 combineAssigns p a =
-    a <> [ModCA . ContAssign (p ^. portName) . fold $ Id <$> assigns]
+    a <> [ModCA . ContAssign (p ^. portName) . UnOp UnXor . fold $ Id <$> assigns]
     where assigns = a ^.. traverse . modContAssign . contAssignNetLVal
 
 combineAssigns_ :: Port -> [Port] -> ModItem
 combineAssigns_ p ps =
     ModCA
         .   ContAssign (p ^. portName)
+        .   UnOp UnXor
         .   fold
         $   Id
         <$> ps