Add new maintainer email

36 files changed, 219 insertions, 297 deletions

diff --git a/src/VeriFuzz.hs b/src/VeriFuzz.hs
index 7bc562f..b3b1ec6 100644
--- a/src/VeriFuzz.hs
+++ b/src/VeriFuzz.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz
 Description : VeriFuzz
 Copyright   : (c) 2018-2019, Yann Herklotz
 License     : BSD-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 -}
@@ -82,7 +82,7 @@ data Opts = Fuzz { fuzzOutput :: {-# UNPACK #-} !Text
                   }
           | Reduce { fileName        :: {-# UNPACK #-} !FilePath
                    , top             :: {-# UNPACK #-} !Text
-                   , reduceScript    :: {-# UNPACK #-} !(Maybe FilePath)
+                   , reduceScript    :: !(Maybe FilePath)
                    , synthesiserDesc :: ![SynthDescription]
                    , rerun           :: Bool
                    }
diff --git a/src/VeriFuzz/Circuit.hs b/src/VeriFuzz/Circuit.hs
index 9ee601f..6083c8e 100644
--- a/src/VeriFuzz/Circuit.hs
+++ b/src/VeriFuzz/Circuit.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Circuit
 Description : Definition of the circuit graph.
 Copyright   : (c) 2018-2019, Yann Herklotz
 License     : BSD-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
@@ -26,8 +26,8 @@ module VeriFuzz.Circuit
 where
 
 import           Control.Lens
-import           Hedgehog                       ( Gen )
-import qualified Hedgehog.Gen                  as Hog
+import           Hedgehog                (Gen)
+import qualified Hedgehog.Gen            as Hog
 import           VeriFuzz.Circuit.Base
 import           VeriFuzz.Circuit.Gen
 import           VeriFuzz.Circuit.Random
diff --git a/src/VeriFuzz/Circuit/Base.hs b/src/VeriFuzz/Circuit/Base.hs
index adc7d52..0bcdf39 100644
--- a/src/VeriFuzz/Circuit/Base.hs
+++ b/src/VeriFuzz/Circuit/Base.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Circuit.Base
 Description : Base types for the circuit module.
 Copyright   : (c) 2019, Yann Herklotz Grave
 License     : GPL-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
@@ -18,10 +18,7 @@ module VeriFuzz.Circuit.Base
     )
 where
 
-import           Data.Graph.Inductive           ( Gr
-                                                , LEdge
-                                                , LNode
-                                                )
+import           Data.Graph.Inductive (Gr, LEdge, LNode)
 import           System.Random
 
 -- | The types for all the gates.
diff --git a/src/VeriFuzz/Circuit/Gen.hs b/src/VeriFuzz/Circuit/Gen.hs
index 323d8bb..eb7cb97 100644
--- a/src/VeriFuzz/Circuit/Gen.hs
+++ b/src/VeriFuzz/Circuit/Gen.hs
@@ -3,7 +3,7 @@ Module      : Verilog.Circuit.Gen
 Description : Generate verilog from circuit.
 Copyright   : (c) 2019, Yann Herklotz Grave
 License     : GPL-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
@@ -15,11 +15,9 @@ module VeriFuzz.Circuit.Gen
     )
 where
 
-import           Data.Graph.Inductive           ( LNode
-                                                , Node
-                                                )
-import qualified Data.Graph.Inductive          as G
-import           Data.Maybe                     ( catMaybes )
+import           Data.Graph.Inductive      (LNode, Node)
+import qualified Data.Graph.Inductive      as G
+import           Data.Maybe                (catMaybes)
 import           VeriFuzz.Circuit.Base
 import           VeriFuzz.Circuit.Internal
 import           VeriFuzz.Verilog.AST
diff --git a/src/VeriFuzz/Circuit/Internal.hs b/src/VeriFuzz/Circuit/Internal.hs
index 5220f4d..17e1586 100644
--- a/src/VeriFuzz/Circuit/Internal.hs
+++ b/src/VeriFuzz/Circuit/Internal.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Circuit.Internal
 Description : Internal helpers for generation.
 Copyright   : (c) 2018-2019, Yann Herklotz
 License     : BSD-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
@@ -19,11 +19,9 @@ module VeriFuzz.Circuit.Internal
     )
 where
 
-import           Data.Graph.Inductive           ( Graph
-                                                , Node
-                                                )
-import qualified Data.Graph.Inductive          as G
-import qualified Data.Text                     as T
+import           Data.Graph.Inductive (Graph, Node)
+import qualified Data.Graph.Inductive as G
+import qualified Data.Text            as T
 
 -- | Convert an integer into a label.
 --
diff --git a/src/VeriFuzz/Circuit/Random.hs b/src/VeriFuzz/Circuit/Random.hs
index 2750de8..fdb5253 100644
--- a/src/VeriFuzz/Circuit/Random.hs
+++ b/src/VeriFuzz/Circuit/Random.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Circuit.Random
 Description : Random generation for DAG
 Copyright   : (c) 2018-2019, Yann Herklotz
 License     : BSD-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
@@ -18,14 +18,13 @@ module VeriFuzz.Circuit.Random
     )
 where
 
-import           Data.Graph.Inductive           ( Context )
-import qualified Data.Graph.Inductive          as G
-import           Data.Graph.Inductive.PatriciaTree
-                                                ( Gr )
-import           Data.List                      ( nub )
-import           Hedgehog                       ( Gen )
-import qualified Hedgehog.Gen                  as Hog
-import qualified Hedgehog.Range                as Hog
+import           Data.Graph.Inductive              (Context)
+import qualified Data.Graph.Inductive              as G
+import           Data.Graph.Inductive.PatriciaTree (Gr)
+import           Data.List                         (nub)
+import           Hedgehog                          (Gen)
+import qualified Hedgehog.Gen                      as Hog
+import qualified Hedgehog.Range                    as Hog
 import           VeriFuzz.Circuit.Base
 
 dupFolder :: (Eq a, Eq b) => Context a b -> [Context a b] -> [Context a b]
diff --git a/src/VeriFuzz/Config.hs b/src/VeriFuzz/Config.hs
index 86daaab..dab854b 100644
--- a/src/VeriFuzz/Config.hs
+++ b/src/VeriFuzz/Config.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Config
 Description : Configuration file format and parser.
 Copyright   : (c) 2019, Yann Herklotz
 License     : GPL-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
diff --git a/src/VeriFuzz/Fuzz.hs b/src/VeriFuzz/Fuzz.hs
index 0eb7f2d..df0ee2d 100644
--- a/src/VeriFuzz/Fuzz.hs
+++ b/src/VeriFuzz/Fuzz.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Fuzz
 Description : Environment to run the simulator and synthesisers in a matrix.
 Copyright   : (c) 2019, Yann Herklotz
 License     : GPL-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
diff --git a/src/VeriFuzz/Internal.hs b/src/VeriFuzz/Internal.hs
index b5ce3ba..c7105fc 100644
--- a/src/VeriFuzz/Internal.hs
+++ b/src/VeriFuzz/Internal.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Internal
 Description : Shared high level code used in the other modules internally.
 Copyright   : (c) 2018-2019, Yann Herklotz
 License     : BSD-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
@@ -20,14 +20,12 @@ module VeriFuzz.Internal
     )
 where
 
-import           Data.ByteString                ( ByteString )
-import           Data.ByteString.Builder        ( byteStringHex
-                                                , toLazyByteString
-                                                )
-import qualified Data.ByteString.Lazy          as L
-import           Data.Text                      ( Text )
-import qualified Data.Text                     as T
-import           Data.Text.Encoding             ( decodeUtf8 )
+import           Data.ByteString         (ByteString)
+import           Data.ByteString.Builder (byteStringHex, toLazyByteString)
+import qualified Data.ByteString.Lazy    as L
+import           Data.Text               (Text)
+import qualified Data.Text               as T
+import           Data.Text.Encoding      (decodeUtf8)
 
 -- | Function to show a bytestring in a hex format.
 showBS :: ByteString -> Text
diff --git a/src/VeriFuzz/Reduce.hs b/src/VeriFuzz/Reduce.hs
index 6bae371..61b7bba 100644
--- a/src/VeriFuzz/Reduce.hs
+++ b/src/VeriFuzz/Reduce.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Reduce
 Description : Test case reducer implementation.
 Copyright   : (c) 2019, Yann Herklotz
 License     : GPL-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
@@ -35,22 +35,18 @@ module VeriFuzz.Reduce
     )
 where
 
-import           Control.Lens            hiding ( (<.>) )
-import           Control.Monad                  ( void )
-import           Control.Monad.IO.Class         ( MonadIO
-                                                , liftIO
-                                                )
-import           Data.Foldable                  ( foldrM )
-import           Data.List                      ( nub )
-import           Data.List.NonEmpty             ( NonEmpty(..) )
-import qualified Data.List.NonEmpty            as NonEmpty
-import           Data.Maybe                     ( mapMaybe )
-import           Data.Text                      ( Text )
-import           Shelly                         ( (<.>) )
+import           Control.Lens            hiding ((<.>))
+import           Control.Monad           (void)
+import           Control.Monad.IO.Class  (MonadIO, liftIO)
+import           Data.Foldable           (foldrM)
+import           Data.List               (nub)
+import           Data.List.NonEmpty      (NonEmpty (..))
+import qualified Data.List.NonEmpty      as NonEmpty
+import           Data.Maybe              (mapMaybe)
+import           Data.Text               (Text)
+import           Shelly                  ((<.>))
 import qualified Shelly
-import           Shelly.Lifted                  ( MonadSh
-                                                , liftSh
-                                                )
+import           Shelly.Lifted           (MonadSh, liftSh)
 import           VeriFuzz.Internal
 import           VeriFuzz.Result
 import           VeriFuzz.Sim
diff --git a/src/VeriFuzz/Report.hs b/src/VeriFuzz/Report.hs
index 3037b34..56fd062 100644
--- a/src/VeriFuzz/Report.hs
+++ b/src/VeriFuzz/Report.hs
@@ -4,7 +4,7 @@ Module      : VeriFuzz.Report
 Description : Generate a report from a fuzz run.
 Copyright   : (c) 2019, Yann Herklotz Grave
 License     : GPL-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
@@ -41,33 +41,23 @@ module VeriFuzz.Report
     )
 where
 
-import           Control.DeepSeq                ( NFData
-                                                , rnf
-                                                )
-import           Control.Lens            hiding ( Identity
-                                                , (<.>)
-                                                )
-import           Data.Bifunctor                 ( bimap )
-import           Data.ByteString                ( ByteString )
-import           Data.Maybe                     ( fromMaybe )
-import           Data.Monoid                    ( Endo )
-import           Data.Text                      ( Text )
+import           Control.DeepSeq               (NFData, rnf)
+import           Control.Lens                  hiding (Identity, (<.>))
+import           Data.Bifunctor                (bimap)
+import           Data.ByteString               (ByteString)
+import           Data.Maybe                    (fromMaybe)
+import           Data.Monoid                   (Endo)
+import           Data.Text                     (Text)
 import qualified Data.Text                     as T
-import           Data.Text.Lazy                 ( toStrict )
+import           Data.Text.Lazy                (toStrict)
 import           Data.Time
-import           Data.Vector                    ( fromList )
-import           Prelude                 hiding ( FilePath )
-import           Shelly                         ( FilePath
-                                                , fromText
-                                                , toTextIgnore
-                                                , (<.>)
-                                                , (</>)
-                                                )
-import           Statistics.Sample              ( meanVariance )
-import           Text.Blaze.Html                ( Html
-                                                , (!)
-                                                )
-import           Text.Blaze.Html.Renderer.Text  ( renderHtml )
+import           Data.Vector                   (fromList)
+import           Prelude                       hiding (FilePath)
+import           Shelly                        (FilePath, fromText,
+                                                toTextIgnore, (<.>), (</>))
+import           Statistics.Sample             (meanVariance)
+import           Text.Blaze.Html               (Html, (!))
+import           Text.Blaze.Html.Renderer.Text (renderHtml)
 import qualified Text.Blaze.Html5              as H
 import qualified Text.Blaze.Html5.Attributes   as A
 import           VeriFuzz.Config
@@ -206,9 +196,9 @@ data FuzzReport = FuzzReport { _fuzzDir      :: !FilePath
                              , _simResults   :: ![SimResult]
                              , _synthStatus  :: ![SynthStatus]
                              , _fileLines    :: {-# UNPACK #-} !Int
-                             , _synthTime    :: {-# UNPACK #-} !NominalDiffTime
-                             , _equivTime    :: {-# UNPACK #-} !NominalDiffTime
-                             , _reducTime    :: {-# UNPACK #-} !NominalDiffTime
+                             , _synthTime    :: !NominalDiffTime
+                             , _equivTime    :: !NominalDiffTime
+                             , _reducTime    :: !NominalDiffTime
                              }
                   deriving (Eq, Show)
 
diff --git a/src/VeriFuzz/Result.hs b/src/VeriFuzz/Result.hs
index 4ea7988..61b1452 100644
--- a/src/VeriFuzz/Result.hs
+++ b/src/VeriFuzz/Result.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Result
 Description : Result monadic type.
 Copyright   : (c) 2019, Yann Herklotz Grave
 License     : GPL-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
@@ -31,14 +31,9 @@ import           Control.Monad.Base
 import           Control.Monad.IO.Class
 import           Control.Monad.Trans.Class
 import           Control.Monad.Trans.Control
-import           Data.Bifunctor                 ( Bifunctor(..) )
-import           Shelly                         ( RunFailed(..)
-                                                , Sh
-                                                , catch_sh
-                                                )
-import           Shelly.Lifted                  ( MonadSh
-                                                , liftSh
-                                                )
+import           Data.Bifunctor              (Bifunctor (..))
+import           Shelly                      (RunFailed (..), Sh, catch_sh)
+import           Shelly.Lifted               (MonadSh, liftSh)
 
 -- | Result type which is equivalent to 'Either' or 'Error'. This is
 -- reimplemented so that there is full control over the 'Monad' definition and
diff --git a/src/VeriFuzz/Sim.hs b/src/VeriFuzz/Sim.hs
index cc9cfef..92d1bc4 100644
--- a/src/VeriFuzz/Sim.hs
+++ b/src/VeriFuzz/Sim.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Sim
 Description : Simulator implementations.
 Copyright   : (c) 2019, Yann Herklotz Grave
 License     : GPL-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
diff --git a/src/VeriFuzz/Sim/Icarus.hs b/src/VeriFuzz/Sim/Icarus.hs
index 8e62136..e7c92dc 100644
--- a/src/VeriFuzz/Sim/Icarus.hs
+++ b/src/VeriFuzz/Sim/Icarus.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Sim.Icarus
 Description : Icarus verilog module.
 Copyright   : (c) 2018-2019, Yann Herklotz
 License     : BSD-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
@@ -17,35 +17,28 @@ module VeriFuzz.Sim.Icarus
     )
 where
 
-import           Control.DeepSeq                ( NFData
-                                                , rnf
-                                                , rwhnf
-                                                )
+import           Control.DeepSeq           (NFData, rnf, rwhnf)
 import           Control.Lens
-import           Control.Monad                  ( void )
-import           Crypto.Hash                    ( Digest
-                                                , hash
-                                                )
-import           Crypto.Hash.Algorithms         ( SHA256 )
-import           Data.Binary                    ( encode )
+import           Control.Monad             (void)
+import           Crypto.Hash               (Digest, hash)
+import           Crypto.Hash.Algorithms    (SHA256)
+import           Data.Binary               (encode)
 import           Data.Bits
-import qualified Data.ByteArray                as BA
-                                                ( convert )
-import           Data.ByteString                ( ByteString )
-import qualified Data.ByteString               as B
-import           Data.ByteString.Lazy           ( toStrict )
-import qualified Data.ByteString.Lazy          as L
-                                                ( ByteString )
-import           Data.Char                      ( digitToInt )
-import           Data.Foldable                  ( fold )
-import           Data.List                      ( transpose )
-import           Data.Maybe                     ( listToMaybe )
-import           Data.Text                      ( Text )
-import qualified Data.Text                     as T
-import           Numeric                        ( readInt )
-import           Prelude                 hiding ( FilePath )
+import qualified Data.ByteArray            as BA (convert)
+import           Data.ByteString           (ByteString)
+import qualified Data.ByteString           as B
+import           Data.ByteString.Lazy      (toStrict)
+import qualified Data.ByteString.Lazy      as L (ByteString)
+import           Data.Char                 (digitToInt)
+import           Data.Foldable             (fold)
+import           Data.List                 (transpose)
+import           Data.Maybe                (listToMaybe)
+import           Data.Text                 (Text)
+import qualified Data.Text                 as T
+import           Numeric                   (readInt)
+import           Prelude                   hiding (FilePath)
 import           Shelly
-import           Shelly.Lifted                  ( liftSh )
+import           Shelly.Lifted             (liftSh)
 import           VeriFuzz.Sim.Internal
 import           VeriFuzz.Sim.Template
 import           VeriFuzz.Verilog.AST
diff --git a/src/VeriFuzz/Sim/Identity.hs b/src/VeriFuzz/Sim/Identity.hs
index 95b4097..bfa99f5 100644
--- a/src/VeriFuzz/Sim/Identity.hs
+++ b/src/VeriFuzz/Sim/Identity.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Sim.Identity
 Description : The identity simulator and synthesiser.
 Copyright   : (c) 2019, Yann Herklotz Grave
 License     : GPL-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
@@ -16,16 +16,11 @@ module VeriFuzz.Sim.Identity
     )
 where
 
-import           Control.DeepSeq                ( NFData
-                                                , rnf
-                                                , rwhnf
-                                                )
-import           Data.Text                      ( Text
-                                                , unpack
-                                                )
-import           Prelude                 hiding ( FilePath )
-import           Shelly                         ( FilePath )
-import           Shelly.Lifted                  ( writefile )
+import           Control.DeepSeq          (NFData, rnf, rwhnf)
+import           Data.Text                (Text, unpack)
+import           Prelude                  hiding (FilePath)
+import           Shelly                   (FilePath)
+import           Shelly.Lifted            (writefile)
 import           VeriFuzz.Sim.Internal
 import           VeriFuzz.Verilog.AST
 import           VeriFuzz.Verilog.CodeGen
diff --git a/src/VeriFuzz/Sim/Internal.hs b/src/VeriFuzz/Sim/Internal.hs
index a05a96f..f5351c7 100644
--- a/src/VeriFuzz/Sim/Internal.hs
+++ b/src/VeriFuzz/Sim/Internal.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Sim.Internal
 Description : Class of the simulator.
 Copyright   : (c) 2018-2019, Yann Herklotz
 License     : BSD-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
@@ -40,26 +40,20 @@ module VeriFuzz.Sim.Internal
 where
 
 import           Control.Lens
-import           Control.Monad                  ( forM
-                                                , void
-                                                )
-import           Control.Monad.Catch            ( throwM )
-import           Data.Bits                      ( shiftL )
-import           Data.ByteString                ( ByteString )
-import qualified Data.ByteString               as B
-import           Data.Maybe                     ( catMaybes )
-import           Data.Text                      ( Text )
-import qualified Data.Text                     as T
-import           Data.Time.Format               ( defaultTimeLocale
-                                                , formatTime
-                                                )
-import           Data.Time.LocalTime            ( getZonedTime )
-import           Prelude                 hiding ( FilePath )
+import           Control.Monad         (forM, void)
+import           Control.Monad.Catch   (throwM)
+import           Data.Bits             (shiftL)
+import           Data.ByteString       (ByteString)
+import qualified Data.ByteString       as B
+import           Data.Maybe            (catMaybes)
+import           Data.Text             (Text)
+import qualified Data.Text             as T
+import           Data.Time.Format      (defaultTimeLocale, formatTime)
+import           Data.Time.LocalTime   (getZonedTime)
+import           Prelude               hiding (FilePath)
 import           Shelly
-import           Shelly.Lifted                  ( MonadSh
-                                                , liftSh
-                                                )
-import           System.FilePath.Posix          ( takeBaseName )
+import           Shelly.Lifted         (MonadSh, liftSh)
+import           System.FilePath.Posix (takeBaseName)
 import           VeriFuzz.Internal
 import           VeriFuzz.Result
 import           VeriFuzz.Verilog.AST
diff --git a/src/VeriFuzz/Sim/Quartus.hs b/src/VeriFuzz/Sim/Quartus.hs
index e0fbba5..254bfa5 100644
--- a/src/VeriFuzz/Sim/Quartus.hs
+++ b/src/VeriFuzz/Sim/Quartus.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Sim.Quartus
 Description : Quartus synthesiser implementation.
 Copyright   : (c) 2019, Yann Herklotz Grave
 License     : GPL-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
@@ -16,16 +16,11 @@ module VeriFuzz.Sim.Quartus
     )
 where
 
-import           Control.DeepSeq                ( NFData
-                                                , rnf
-                                                , rwhnf
-                                                )
-import           Data.Text                      ( Text
-                                                , unpack
-                                                )
-import           Prelude                 hiding ( FilePath )
+import           Control.DeepSeq          (NFData, rnf, rwhnf)
+import           Data.Text                (Text, unpack)
+import           Prelude                  hiding (FilePath)
 import           Shelly
-import           Shelly.Lifted                  ( liftSh )
+import           Shelly.Lifted            (liftSh)
 import           VeriFuzz.Sim.Internal
 import           VeriFuzz.Verilog.AST
 import           VeriFuzz.Verilog.CodeGen
diff --git a/src/VeriFuzz/Sim/Template.hs b/src/VeriFuzz/Sim/Template.hs
index 3be6558..9b8ee9f 100644
--- a/src/VeriFuzz/Sim/Template.hs
+++ b/src/VeriFuzz/Sim/Template.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Sim.Template
 Description : Template file for different configuration files
 Copyright   : (c) 2019, Yann Herklotz
 License     : GPL-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
diff --git a/src/VeriFuzz/Sim/Vivado.hs b/src/VeriFuzz/Sim/Vivado.hs
index 8697a0f..4ddb048 100644
--- a/src/VeriFuzz/Sim/Vivado.hs
+++ b/src/VeriFuzz/Sim/Vivado.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Sim.Vivado
 Description : Vivado Synthesiser implementation.
 Copyright   : (c) 2019, Yann Herklotz Grave
 License     : GPL-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
@@ -16,16 +16,11 @@ module VeriFuzz.Sim.Vivado
     )
 where
 
-import           Control.DeepSeq                ( NFData
-                                                , rnf
-                                                , rwhnf
-                                                )
-import           Data.Text                      ( Text
-                                                , unpack
-                                                )
-import           Prelude                 hiding ( FilePath )
+import           Control.DeepSeq          (NFData, rnf, rwhnf)
+import           Data.Text                (Text, unpack)
+import           Prelude                  hiding (FilePath)
 import           Shelly
-import           Shelly.Lifted                  ( liftSh )
+import           Shelly.Lifted            (liftSh)
 import           VeriFuzz.Sim.Internal
 import           VeriFuzz.Sim.Template
 import           VeriFuzz.Verilog.AST
diff --git a/src/VeriFuzz/Sim/XST.hs b/src/VeriFuzz/Sim/XST.hs
index f5faae5..86db667 100644
--- a/src/VeriFuzz/Sim/XST.hs
+++ b/src/VeriFuzz/Sim/XST.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Sim.XST
 Description : XST (ise) simulator implementation.
 Copyright   : (c) 2018-2019, Yann Herklotz
 License     : BSD-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
@@ -18,17 +18,12 @@ module VeriFuzz.Sim.XST
     )
 where
 
-import           Control.DeepSeq                ( NFData
-                                                , rnf
-                                                , rwhnf
-                                                )
-import           Data.Text                      ( Text
-                                                , unpack
-                                                )
-import           Prelude                 hiding ( FilePath )
+import           Control.DeepSeq          (NFData, rnf, rwhnf)
+import           Data.Text                (Text, unpack)
+import           Prelude                  hiding (FilePath)
 import           Shelly
-import           Shelly.Lifted                  ( liftSh )
-import           Text.Shakespeare.Text          ( st )
+import           Shelly.Lifted            (liftSh)
+import           Text.Shakespeare.Text    (st)
 import           VeriFuzz.Sim.Internal
 import           VeriFuzz.Sim.Template
 import           VeriFuzz.Verilog.AST
diff --git a/src/VeriFuzz/Sim/Yosys.hs b/src/VeriFuzz/Sim/Yosys.hs
index 8f9d4a7..d69bc69 100644
--- a/src/VeriFuzz/Sim/Yosys.hs
+++ b/src/VeriFuzz/Sim/Yosys.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Sim.Yosys
 Description : Yosys simulator implementation.
 Copyright   : (c) 2018-2019, Yann Herklotz
 License     : BSD-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
@@ -20,19 +20,14 @@ module VeriFuzz.Sim.Yosys
     )
 where
 
-import           Control.DeepSeq                ( NFData
-                                                , rnf
-                                                , rwhnf
-                                                )
+import           Control.DeepSeq          (NFData, rnf, rwhnf)
 import           Control.Lens
-import           Control.Monad                  ( void )
-import           Data.Text                      ( Text
-                                                , unpack
-                                                )
-import           Prelude                 hiding ( FilePath )
+import           Control.Monad            (void)
+import           Data.Text                (Text, unpack)
+import           Prelude                  hiding (FilePath)
 import           Shelly
-import           Shelly.Lifted                  ( liftSh )
-import           Text.Shakespeare.Text          ( st )
+import           Shelly.Lifted            (liftSh)
+import           Text.Shakespeare.Text    (st)
 import           VeriFuzz.Result
 import           VeriFuzz.Sim.Internal
 import           VeriFuzz.Sim.Template
diff --git a/src/VeriFuzz/Verilog.hs b/src/VeriFuzz/Verilog.hs
index 628b00a..7d7eea6 100644
--- a/src/VeriFuzz/Verilog.hs
+++ b/src/VeriFuzz/Verilog.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Verilog
 Description : Verilog implementation with random generation and mutations.
 Copyright   : (c) 2019, Yann Herklotz Grave
 License     : GPL-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs
index 43063e6..e90d388 100644
--- a/src/VeriFuzz/Verilog/AST.hs
+++ b/src/VeriFuzz/Verilog/AST.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Verilog.AST
 Description : Definition of the Verilog AST types.
 Copyright   : (c) 2018-2019, Yann Herklotz
 License     : BSD-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Poratbility : POSIX
 
@@ -139,18 +139,14 @@ module VeriFuzz.Verilog.AST
     )
 where
 
-import           Control.Lens            hiding ( (<|) )
+import           Control.Lens             hiding ((<|))
 import           Data.Data
 import           Data.Data.Lens
-import           Data.Functor.Foldable.TH       ( makeBaseFunctor )
-import           Data.List.NonEmpty             ( NonEmpty(..)
-                                                , (<|)
-                                                )
-import           Data.String                    ( IsString
-                                                , fromString
-                                                )
-import           Data.Text                      ( Text )
-import           Data.Traversable               ( sequenceA )
+import           Data.Functor.Foldable.TH (makeBaseFunctor)
+import           Data.List.NonEmpty       (NonEmpty (..), (<|))
+import           Data.String              (IsString, fromString)
+import           Data.Text                (Text)
+import           Data.Traversable         (sequenceA)
 import           VeriFuzz.Verilog.BitVec
 
 -- | Identifier in Verilog. This is just a string of characters that can either
diff --git a/src/VeriFuzz/Verilog/BitVec.hs b/src/VeriFuzz/Verilog/BitVec.hs
index cdae0f7..80fa539 100644
--- a/src/VeriFuzz/Verilog/BitVec.hs
+++ b/src/VeriFuzz/Verilog/BitVec.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Verilog.BitVec
 Description : Unsigned BitVec implementation.
 Copyright   : (c) 2019, Yann Herklotz Grave
 License     : GPL-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs
index 82945aa..56e2819 100644
--- a/src/VeriFuzz/Verilog/CodeGen.hs
+++ b/src/VeriFuzz/Verilog/CodeGen.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Verilog.CodeGen
 Description : Code generation for Verilog AST.
 Copyright   : (c) 2018-2019, Yann Herklotz
 License     : BSD-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
@@ -22,15 +22,13 @@ module VeriFuzz.Verilog.CodeGen
     )
 where
 
-import           Data.Data                      ( Data )
-import           Data.List.NonEmpty             ( NonEmpty(..)
-                                                , toList
-                                                )
-import           Data.Text                      ( Text )
-import qualified Data.Text                     as T
+import           Data.Data                 (Data)
+import           Data.List.NonEmpty        (NonEmpty (..), toList)
+import           Data.Text                 (Text)
+import qualified Data.Text                 as T
 import           Data.Text.Prettyprint.Doc
-import           Numeric                        ( showHex )
-import           VeriFuzz.Internal       hiding ( comma )
+import           Numeric                   (showHex)
+import           VeriFuzz.Internal         hiding (comma)
 import           VeriFuzz.Verilog.AST
 import           VeriFuzz.Verilog.BitVec
 
diff --git a/src/VeriFuzz/Verilog/Eval.hs b/src/VeriFuzz/Verilog/Eval.hs
index d8840e3..c802267 100644
--- a/src/VeriFuzz/Verilog/Eval.hs
+++ b/src/VeriFuzz/Verilog/Eval.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Verilog.Eval
 Description : Evaluation of Verilog expressions and statements.
 Copyright   : (c) 2019, Yann Herklotz Grave
 License     : GPL-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
@@ -17,9 +17,9 @@ module VeriFuzz.Verilog.Eval
 where
 
 import           Data.Bits
-import           Data.Foldable                  ( fold )
-import           Data.Functor.Foldable   hiding ( fold )
-import           Data.Maybe                     ( listToMaybe )
+import           Data.Foldable           (fold)
+import           Data.Functor.Foldable   hiding (fold)
+import           Data.Maybe              (listToMaybe)
 import           VeriFuzz.Verilog.AST
 import           VeriFuzz.Verilog.BitVec
 
diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs
index 458878b..6cb6eb1 100644
--- a/src/VeriFuzz/Verilog/Gen.hs
+++ b/src/VeriFuzz/Verilog/Gen.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Verilog.Gen
 Description : Various useful generators.
 Copyright   : (c) 2019, Yann Herklotz
 License     : GPL-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
@@ -30,7 +30,7 @@ import           Control.Monad.Trans.Reader       hiding (local)
 import           Control.Monad.Trans.State.Strict
 import           Data.Foldable                    (fold)
 import           Data.Functor.Foldable            (cata)
-import           Data.List                        (foldl')
+import           Data.List                        (foldl', partition)
 import qualified Data.Text                        as T
 import           Hedgehog                         (Gen)
 import qualified Hedgehog.Gen                     as Hog
@@ -44,6 +44,7 @@ import           VeriFuzz.Verilog.Internal
 import           VeriFuzz.Verilog.Mutate
 
 -- Temporary imports
+import           Data.Char                        (toLower)
 import           Debug.Trace
 import           VeriFuzz.Verilog.CodeGen
 
@@ -353,18 +354,23 @@ alwaysSeq = Always . EventCtrl (EPosEdge "clk") . Just <$> seqBlock
 resizePort :: [Parameter] -> Identifier -> Range -> [Port] -> [Port]
 resizePort ps i ra = foldl' func []
     where
-        func l p@(Port _ _ ri i')
-            | i' == i && calc ri < calc ra = (p & portSize .~ ra) : l
+        func l p@(Port t _ ri i')
+            | i' == i && calc ri < calc ra = trace (fmap toLower (show t) <> " " <> show (GenVerilog i) <> ": " <> (show $ calc ri) <> " to " <> (show $ calc ra)) $ (p & portSize .~ ra) : l
             | otherwise = p : l
         calc = calcRange ps $ Just 64
 
 -- | Instantiate a module, where the outputs are new nets that are created, and
 -- the inputs are taken from existing ports in the context.
+--
+-- 1 is subtracted from the inputs for the length because the clock is not
+-- counted and is assumed to be there, this should be made nicer by filtering
+-- out the clock instead. I think that in general there should be a special
+-- representation for the clock.
 instantiate :: ModDecl -> StateGen ModItem
 instantiate (ModDecl i outP inP _ _) = do
     context <- get
     outs    <- replicateM (length outP) (nextPort Wire)
-    ins <- take (length inP) <$> Hog.shuffle (context ^. variables)
+    ins <- take (length inP - 1) <$> Hog.shuffle (context ^. variables)
     mapM_ (uncurry process) . zip (ins ^.. traverse . portName) $ inP ^.. traverse . portSize
     ident <- makeIdentifier "modinst"
     vs <- view variables <$> get
@@ -466,8 +472,8 @@ calcRange ps i (Range l r) = eval l - eval r + 1
   where
     eval a = fromIntegral . cata (evaluateConst ps) $ maybe a (`resize` a) i
 
-notIdentElem :: Port -> [Port] -> Bool
-notIdentElem p = notElem (p ^. portName) . toListOf (traverse . portName)
+identElem :: Port -> [Port] -> Bool
+identElem p = elem (p ^. portName) . toListOf (traverse . portName)
 
 -- | Generates a module definition randomly. It always has one output port which
 -- is set to @y@. The size of @y@ is the total combination of all the locally
@@ -481,7 +487,7 @@ moduleDef top = do
     ps       <- Hog.list (Hog.linear 0 10) parameter
     context  <- get
     config   <- lift ask
-    let local = filter (`notIdentElem` portList) $ _variables context
+    let (newPorts, local) = partition (`identElem` portList) $ _variables context
     let
         size =
             evalRange (_parameters context) 32
@@ -496,7 +502,7 @@ moduleDef top = do
     let comb = combineAssigns_ combine yport local
     return
         . declareMod local
-        . ModDecl name [yport] (clock : portList) (comb : mi)
+        . ModDecl name [yport] (clock : newPorts) (comb : mi)
         $ ps
 
 -- | Procedural generation method for random Verilog. Uses internal 'Reader' and
diff --git a/src/VeriFuzz/Verilog/Internal.hs b/src/VeriFuzz/Verilog/Internal.hs
index 16148cf..42eb4e2 100644
--- a/src/VeriFuzz/Verilog/Internal.hs
+++ b/src/VeriFuzz/Verilog/Internal.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Verilog.Internal
 Description : Defaults and common functions.
 Copyright   : (c) 2018-2019, Yann Herklotz
 License     : BSD-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
@@ -29,7 +29,7 @@ module VeriFuzz.Verilog.Internal
 where
 
 import           Control.Lens
-import           Data.Text                      ( Text )
+import           Data.Text            (Text)
 import           VeriFuzz.Verilog.AST
 
 regDecl :: Identifier -> ModItem
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs
index e4a10df..37d3a7d 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Verilog/Mutate.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Verilog.Mutate
 Description : Functions to mutate the Verilog AST.
 Copyright   : (c) 2018-2019, Yann Herklotz
 License     : BSD-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
@@ -41,12 +41,10 @@ module VeriFuzz.Verilog.Mutate
 where
 
 import           Control.Lens
-import           Data.Foldable                  ( fold )
-import           Data.Maybe                     ( catMaybes
-                                                , fromMaybe
-                                                )
-import           Data.Text                      ( Text )
-import qualified Data.Text                     as T
+import           Data.Foldable             (fold)
+import           Data.Maybe                (catMaybes, fromMaybe)
+import           Data.Text                 (Text)
+import qualified Data.Text                 as T
 import           VeriFuzz.Circuit.Internal
 import           VeriFuzz.Internal
 import           VeriFuzz.Verilog.AST
@@ -323,11 +321,10 @@ makeTopAssert = (modItems %~ (++ [assert])) . makeTop 2
 -- | Provide declarations for all the ports that are passed to it. If they are
 -- registers, it should assign them to 0.
 declareMod :: [Port] -> ModDecl -> ModDecl
-declareMod ports = initMod . (modItems %~ (decl ++))
+declareMod ports = initMod . (modItems %~ (fmap decl ports ++))
   where
-    decl = declf <$> ports
-    declf p@(Port Reg _ _ _) = Decl Nothing p (Just 0)
-    declf p                  = Decl Nothing p Nothing
+    decl p@(Port Reg _ _ _) = Decl Nothing p (Just 0)
+    decl p                  = Decl Nothing p Nothing
 
 -- | Simplify an 'Expr' by using constants to remove 'BinaryOperator' and
 -- simplify expressions. To make this work effectively, it should be run until
@@ -339,30 +336,30 @@ declareMod ports = initMod . (modItems %~ (decl ++))
 -- >>> GenVerilog . simplify $ (Id "y") + (Id "x")
 -- (y + x)
 simplify :: Expr -> Expr
-simplify (BinOp (Number (BitVec _ 1)) BinAnd e) = e
-simplify (BinOp e BinAnd (Number (BitVec _ 1))) = e
-simplify (BinOp (Number (BitVec _ 0)) BinAnd _) = Number 0
-simplify (BinOp _ BinAnd (Number (BitVec _ 0))) = Number 0
-simplify (BinOp e BinPlus (Number (BitVec _ 0))) = e
-simplify (BinOp (Number (BitVec _ 0)) BinPlus e) = e
+simplify (BinOp (Number (BitVec _ 1)) BinAnd e)   = e
+simplify (BinOp e BinAnd (Number (BitVec _ 1)))   = e
+simplify (BinOp (Number (BitVec _ 0)) BinAnd _)   = Number 0
+simplify (BinOp _ BinAnd (Number (BitVec _ 0)))   = Number 0
+simplify (BinOp e BinPlus (Number (BitVec _ 0)))  = e
+simplify (BinOp (Number (BitVec _ 0)) BinPlus e)  = e
 simplify (BinOp e BinMinus (Number (BitVec _ 0))) = e
 simplify (BinOp (Number (BitVec _ 0)) BinMinus e) = e
 simplify (BinOp e BinTimes (Number (BitVec _ 1))) = e
 simplify (BinOp (Number (BitVec _ 1)) BinTimes e) = e
 simplify (BinOp _ BinTimes (Number (BitVec _ 0))) = Number 0
 simplify (BinOp (Number (BitVec _ 0)) BinTimes _) = Number 0
-simplify (BinOp e BinOr (Number (BitVec _ 0))) = e
-simplify (BinOp (Number (BitVec _ 0)) BinOr e) = e
-simplify (BinOp e BinLSL (Number (BitVec _ 0))) = e
-simplify (BinOp (Number (BitVec _ 0)) BinLSL e) = e
-simplify (BinOp e BinLSR (Number (BitVec _ 0))) = e
-simplify (BinOp (Number (BitVec _ 0)) BinLSR e) = e
-simplify (BinOp e BinASL (Number (BitVec _ 0))) = e
-simplify (BinOp (Number (BitVec _ 0)) BinASL e) = e
-simplify (BinOp e BinASR (Number (BitVec _ 0))) = e
-simplify (BinOp (Number (BitVec _ 0)) BinASR e) = e
-simplify (UnOp UnPlus e) = e
-simplify e               = e
+simplify (BinOp e BinOr (Number (BitVec _ 0)))    = e
+simplify (BinOp (Number (BitVec _ 0)) BinOr e)    = e
+simplify (BinOp e BinLSL (Number (BitVec _ 0)))   = e
+simplify (BinOp (Number (BitVec _ 0)) BinLSL e)   = e
+simplify (BinOp e BinLSR (Number (BitVec _ 0)))   = e
+simplify (BinOp (Number (BitVec _ 0)) BinLSR e)   = e
+simplify (BinOp e BinASL (Number (BitVec _ 0)))   = e
+simplify (BinOp (Number (BitVec _ 0)) BinASL e)   = e
+simplify (BinOp e BinASR (Number (BitVec _ 0)))   = e
+simplify (BinOp (Number (BitVec _ 0)) BinASR e)   = e
+simplify (UnOp UnPlus e)                          = e
+simplify e                                        = e
 
 -- | Remove all 'Identifier' that do not appeare in the input list from an
 -- 'Expr'. The identifier will be replaced by @1'b0@, which can then later be
diff --git a/src/VeriFuzz/Verilog/Parser.hs b/src/VeriFuzz/Verilog/Parser.hs
index 0820e48..c08ebcd 100644
--- a/src/VeriFuzz/Verilog/Parser.hs
+++ b/src/VeriFuzz/Verilog/Parser.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Verilog.Parser
 Description : Minimal Verilog parser to reconstruct the AST.
 Copyright   : (c) 2019, Yann Herklotz
 License     : GPL-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
@@ -26,20 +26,17 @@ module VeriFuzz.Verilog.Parser
 where
 
 import           Control.Lens
-import           Control.Monad                  ( void )
-import           Data.Bifunctor                 ( bimap )
+import           Control.Monad               (void)
+import           Data.Bifunctor              (bimap)
 import           Data.Bits
-import           Data.Functor                   ( ($>) )
-import           Data.Functor.Identity          ( Identity )
-import           Data.List                      ( isInfixOf
-                                                , isPrefixOf
-                                                , null
-                                                )
-import           Data.List.NonEmpty             ( NonEmpty(..) )
-import           Data.Text                      ( Text )
-import qualified Data.Text                     as T
-import qualified Data.Text.IO                  as T
-import           Text.Parsec             hiding ( satisfy )
+import           Data.Functor                (($>))
+import           Data.Functor.Identity       (Identity)
+import           Data.List                   (isInfixOf, isPrefixOf, null)
+import           Data.List.NonEmpty          (NonEmpty (..))
+import           Data.Text                   (Text)
+import qualified Data.Text                   as T
+import qualified Data.Text.IO                as T
+import           Text.Parsec                 hiding (satisfy)
 import           Text.Parsec.Expr
 import           VeriFuzz.Internal
 import           VeriFuzz.Verilog.AST
diff --git a/src/VeriFuzz/Verilog/Preprocess.hs b/src/VeriFuzz/Verilog/Preprocess.hs
index 6e9305a..c783ac5 100644
--- a/src/VeriFuzz/Verilog/Preprocess.hs
+++ b/src/VeriFuzz/Verilog/Preprocess.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Verilog.Preprocess
 Description : Simple preprocessor for `define and comments.
 Copyright   : (c) 2011-2015 Tom Hawkins, 2019 Yann Herklotz
 License     : GPL-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
diff --git a/src/VeriFuzz/Verilog/Quote.hs b/src/VeriFuzz/Verilog/Quote.hs
index f0b7c96..c6d3e3c 100644
--- a/src/VeriFuzz/Verilog/Quote.hs
+++ b/src/VeriFuzz/Verilog/Quote.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Verilog.Quote
 Description : QuasiQuotation for verilog code in Haskell.
 Copyright   : (c) 2019, Yann Herklotz Grave
 License     : GPL-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
@@ -18,8 +18,8 @@ module VeriFuzz.Verilog.Quote
 where
 
 import           Data.Data
-import qualified Data.Text                     as T
-import qualified Language.Haskell.TH           as TH
+import qualified Data.Text                  as T
+import qualified Language.Haskell.TH        as TH
 import           Language.Haskell.TH.Quote
 import           Language.Haskell.TH.Syntax
 import           VeriFuzz.Verilog.Parser
diff --git a/src/VeriFuzz/Verilog/Token.hs b/src/VeriFuzz/Verilog/Token.hs
index 65c2319..d69f0b3 100644
--- a/src/VeriFuzz/Verilog/Token.hs
+++ b/src/VeriFuzz/Verilog/Token.hs
@@ -3,7 +3,7 @@ Module      : VeriFuzz.Verilog.Token
 Description : Tokens for Verilog parsing.
 Copyright   : (c) 2019, Yann Herklotz Grave
 License     : GPL-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
diff --git a/test/Parser.hs b/test/Parser.hs
index 84f1906..d300d8a 100644
--- a/test/Parser.hs
+++ b/test/Parser.hs
@@ -3,7 +3,7 @@ Module      : Parser
 Description : Test the parser.
 Copyright   : (c) 2019, Yann Herklotz Grave
 License     : GPL-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
@@ -17,15 +17,10 @@ module Parser
 where
 
 import           Control.Lens
-import           Data.Either                    ( either
-                                                , isRight
-                                                )
-import           Hedgehog                       ( Gen
-                                                , Property
-                                                , (===)
-                                                )
-import qualified Hedgehog                      as Hog
-import qualified Hedgehog.Gen                  as Hog
+import           Data.Either             (either, isRight)
+import           Hedgehog                (Gen, Property, (===))
+import qualified Hedgehog                as Hog
+import qualified Hedgehog.Gen            as Hog
 import           Test.Tasty
 import           Test.Tasty.Hedgehog
 import           Test.Tasty.HUnit
diff --git a/test/Reduce.hs b/test/Reduce.hs
index bc47d94..722ddea 100644
--- a/test/Reduce.hs
+++ b/test/Reduce.hs
@@ -3,7 +3,7 @@ Module      : Reduce
 Description : Test reduction.
 Copyright   : (c) 2019, Yann Herklotz Grave
 License     : GPL-3
-Maintainer  : ymherklotz [at] gmail [dot] com
+Maintainer  : yann [at] yannherklotz [dot] com
 Stability   : experimental
 Portability : POSIX
 
@@ -17,7 +17,7 @@ module Reduce
     )
 where
 
-import           Data.List                      ( (\\) )
+import           Data.List        ((\\))
 import           Test.Tasty
 import           Test.Tasty.HUnit
 import           VeriFuzz
diff --git a/verifuzz.cabal b/verifuzz.cabal
index 374d133..1a8b573 100644
--- a/verifuzz.cabal
+++ b/verifuzz.cabal
@@ -8,7 +8,7 @@ homepage: https://github.com/ymherklotz/VeriFuzz#readme
 license: BSD3
 license-file: LICENSE
 author: Yann Herklotz
-maintainer: yann [at] ymhg [dot] org
+maintainer: yann [at] yannherklotz [dot] com
 copyright: 2018 Yann Herklotz
 category: Web
 build-type: Custom