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| author | Yann Herklotz <git@yannherklotz.com> | 2019-06-05 12:06:49 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-06-05 12:06:49 +0100 |
| commit | c40faa081ae7f31cb1b6125d1c5c3bdf650f3f63 (patch) | |
| tree | 3e3bb7026ba268eed2f842d702195b0472c905d2 | |
| parent | e4737c37c9dc358d56dbb7a97d68de2c93053c0c (diff) | |
| download | verismith-c40faa081ae7f31cb1b6125d1c5c3bdf650f3f63.tar.gz verismith-c40faa081ae7f31cb1b6125d1c5c3bdf650f3f63.zip | |
Add combination option
| -rw-r--r-- | src/VeriFuzz/Config.hs | 6 | ||||
| -rw-r--r-- | src/VeriFuzz/Verilog/Gen.hs | 3 | ||||
| -rw-r--r-- | src/VeriFuzz/Verilog/Mutate.hs | 6 |
3 files changed, 10 insertions, 5 deletions
diff --git a/src/VeriFuzz/Config.hs b/src/VeriFuzz/Config.hs index 375c739..dd61d31 100644 --- a/src/VeriFuzz/Config.hs +++ b/src/VeriFuzz/Config.hs @@ -68,6 +68,7 @@ module VeriFuzz.Config , propStmntDepth , propModDepth , propMaxModules + , propCombine , parseConfigFile , parseConfig , encodeConfig @@ -198,6 +199,7 @@ data ConfProperty = ConfProperty { _propSize :: {-# UNPACK #-} !Int , _propMaxModules :: {-# UNPACK #-} !Int , _propSampleMethod :: !Text , _propSampleSize :: {-# UNPACK #-} !Int + , _propCombine :: {-# UNPACK #-} !Bool } deriving (Eq, Show) @@ -265,7 +267,7 @@ defaultConfig :: Config defaultConfig = Config (Info (pack $(gitHash)) (pack $ showVersion version)) (Probability defModItem defStmnt defExpr) - (ConfProperty 20 Nothing 3 2 5 "random" 10) + (ConfProperty 20 Nothing 3 2 5 "random" 10 False) [] [fromYosys defaultYosys, fromVivado defaultVivado] where @@ -382,6 +384,8 @@ propCodec = .= _propSampleMethod <*> defaultValue (defProp propSampleSize) (int "sample" "size") .= _propSampleSize + <*> defaultValue (defProp propCombine) (Toml.bool (twoKey "output" "combine")) + .= _propCombine where defProp i = defaultConfig ^. configProperty . i simulator :: TomlCodec SimDescription diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs index c903e28..cb3a8ad 100644 --- a/src/VeriFuzz/Verilog/Gen.hs +++ b/src/VeriFuzz/Verilog/Gen.hs @@ -455,6 +455,7 @@ moduleDef top = do mi <- Hog.list (Hog.linear 4 100) modItem ps <- Hog.list (Hog.linear 0 10) parameter context <- get + config <- lift ask let local = filter (`notElem` portList) $ _variables context let size = @@ -465,7 +466,7 @@ moduleDef top = do . portSize let clock = Port Wire False 1 "clk" let yport = if True then Port Wire False 1 "y" else Port Wire False size "y" - let comb = combineAssigns_ yport local + let comb = combineAssigns_ (config ^. configProperty . propCombine) yport local return . declareMod local . ModDecl name [yport] (clock : portList) (comb : mi) diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index 8af0182..7496935 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -380,11 +380,11 @@ combineAssigns p a = a <> [ModCA . ContAssign (p ^. portName) . UnOp UnXor . fold $ Id <$> assigns] where assigns = a ^.. traverse . modContAssign . contAssignNetLVal -combineAssigns_ :: Port -> [Port] -> ModItem -combineAssigns_ p ps = +combineAssigns_ :: Bool -> Port -> [Port] -> ModItem +combineAssigns_ comb p ps = ModCA . ContAssign (p ^. portName) - . UnOp UnXor + . (if comb then UnOp UnXor else id) . fold $ Id <$> ps |