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authorYann Herklotz <git@yannherklotz.com>2019-06-29 20:33:59 +0100
committerYann Herklotz <git@yannherklotz.com>2019-06-29 20:33:59 +0100
commitd32f4cc45bc8c0670fb788b1fcd4c2f2b15fa094 (patch)
tree9aee938477a884daa20148b56fc1feef52d4f2c4
parentbb697f8bc7b593e5aabb43505f686e6503b7726f (diff)
downloadverismith-d32f4cc45bc8c0670fb788b1fcd4c2f2b15fa094.tar.gz
verismith-d32f4cc45bc8c0670fb788b1fcd4c2f2b15fa094.zip
Format files
-rw-r--r--src/VeriFuzz.hs44
-rw-r--r--src/VeriFuzz/Circuit.hs4
-rw-r--r--src/VeriFuzz/Circuit/Base.hs5
-rw-r--r--src/VeriFuzz/Circuit/Gen.hs8
-rw-r--r--src/VeriFuzz/Circuit/Internal.hs8
-rw-r--r--src/VeriFuzz/Circuit/Random.hs15
-rw-r--r--src/VeriFuzz/Config.hs26
-rw-r--r--src/VeriFuzz/Fuzz.hs96
-rw-r--r--src/VeriFuzz/Internal.hs14
-rw-r--r--src/VeriFuzz/Reduce.hs26
-rw-r--r--src/VeriFuzz/Report.hs40
-rw-r--r--src/VeriFuzz/Result.hs11
-rw-r--r--src/VeriFuzz/Sim/Icarus.hs116
-rw-r--r--src/VeriFuzz/Sim/Identity.hs15
-rw-r--r--src/VeriFuzz/Sim/Internal.hs32
-rw-r--r--src/VeriFuzz/Sim/Quartus.hs13
-rw-r--r--src/VeriFuzz/Sim/Vivado.hs13
-rw-r--r--src/VeriFuzz/Sim/XST.hs15
-rw-r--r--src/VeriFuzz/Sim/Yosys.hs17
-rw-r--r--src/VeriFuzz/Verilog/AST.hs16
-rw-r--r--src/VeriFuzz/Verilog/CodeGen.hs14
-rw-r--r--src/VeriFuzz/Verilog/Eval.hs6
-rw-r--r--src/VeriFuzz/Verilog/Gen.hs21
-rw-r--r--src/VeriFuzz/Verilog/Internal.hs2
-rw-r--r--src/VeriFuzz/Verilog/Mutate.hs46
-rw-r--r--src/VeriFuzz/Verilog/Parser.hs23
-rw-r--r--src/VeriFuzz/Verilog/Quote.hs4
-rw-r--r--test/Doctest.hs7
-rw-r--r--test/Parser.hs13
-rw-r--r--test/Property.hs27
-rw-r--r--test/Reduce.hs2
-rw-r--r--test/Unit.hs6
32 files changed, 416 insertions, 289 deletions
diff --git a/src/VeriFuzz.hs b/src/VeriFuzz.hs
index 7bc562f..0bbdc4f 100644
--- a/src/VeriFuzz.hs
+++ b/src/VeriFuzz.hs
@@ -28,27 +28,29 @@ module VeriFuzz
where
import Control.Concurrent
-import Control.Lens hiding ((<.>))
-import Control.Monad.IO.Class (liftIO)
-import qualified Crypto.Random.DRBG as C
-import Data.ByteString (ByteString)
-import Data.ByteString.Builder (byteStringHex, toLazyByteString)
-import qualified Data.ByteString.Lazy as L
-import qualified Data.Graph.Inductive as G
-import qualified Data.Graph.Inductive.Dot as G
-import Data.Maybe (isNothing)
-import Data.Text (Text)
-import qualified Data.Text as T
-import Data.Text.Encoding (decodeUtf8)
-import qualified Data.Text.IO as T
-import Hedgehog (Gen)
-import qualified Hedgehog.Gen as Hog
-import Hedgehog.Internal.Seed (Seed)
+import Control.Lens hiding ( (<.>) )
+import Control.Monad.IO.Class ( liftIO )
+import qualified Crypto.Random.DRBG as C
+import Data.ByteString ( ByteString )
+import Data.ByteString.Builder ( byteStringHex
+ , toLazyByteString
+ )
+import qualified Data.ByteString.Lazy as L
+import qualified Data.Graph.Inductive as G
+import qualified Data.Graph.Inductive.Dot as G
+import Data.Maybe ( isNothing )
+import Data.Text ( Text )
+import qualified Data.Text as T
+import Data.Text.Encoding ( decodeUtf8 )
+import qualified Data.Text.IO as T
+import Hedgehog ( Gen )
+import qualified Hedgehog.Gen as Hog
+import Hedgehog.Internal.Seed ( Seed )
import Options.Applicative
-import Prelude hiding (FilePath)
-import Shelly hiding (command)
-import Shelly.Lifted (liftSh)
-import System.Random (randomIO)
+import Prelude hiding ( FilePath )
+import Shelly hiding ( command )
+import Shelly.Lifted ( liftSh )
+import System.Random ( randomIO )
import VeriFuzz.Circuit
import VeriFuzz.Config
import VeriFuzz.Fuzz
@@ -58,7 +60,7 @@ import VeriFuzz.Result
import VeriFuzz.Sim
import VeriFuzz.Sim.Internal
import VeriFuzz.Verilog
-import VeriFuzz.Verilog.Parser (parseSourceInfoFile)
+import VeriFuzz.Verilog.Parser ( parseSourceInfoFile )
data OptTool = TYosys
| TXST
diff --git a/src/VeriFuzz/Circuit.hs b/src/VeriFuzz/Circuit.hs
index 58027b1..9ee601f 100644
--- a/src/VeriFuzz/Circuit.hs
+++ b/src/VeriFuzz/Circuit.hs
@@ -26,8 +26,8 @@ module VeriFuzz.Circuit
where
import Control.Lens
-import Hedgehog (Gen)
-import qualified Hedgehog.Gen as Hog
+import Hedgehog ( Gen )
+import qualified Hedgehog.Gen as Hog
import VeriFuzz.Circuit.Base
import VeriFuzz.Circuit.Gen
import VeriFuzz.Circuit.Random
diff --git a/src/VeriFuzz/Circuit/Base.hs b/src/VeriFuzz/Circuit/Base.hs
index ed63105..adc7d52 100644
--- a/src/VeriFuzz/Circuit/Base.hs
+++ b/src/VeriFuzz/Circuit/Base.hs
@@ -18,7 +18,10 @@ module VeriFuzz.Circuit.Base
)
where
-import Data.Graph.Inductive (Gr, LEdge, LNode)
+import Data.Graph.Inductive ( Gr
+ , LEdge
+ , LNode
+ )
import System.Random
-- | The types for all the gates.
diff --git a/src/VeriFuzz/Circuit/Gen.hs b/src/VeriFuzz/Circuit/Gen.hs
index 0b13ece..323d8bb 100644
--- a/src/VeriFuzz/Circuit/Gen.hs
+++ b/src/VeriFuzz/Circuit/Gen.hs
@@ -15,9 +15,11 @@ module VeriFuzz.Circuit.Gen
)
where
-import Data.Graph.Inductive (LNode, Node)
-import qualified Data.Graph.Inductive as G
-import Data.Maybe (catMaybes)
+import Data.Graph.Inductive ( LNode
+ , Node
+ )
+import qualified Data.Graph.Inductive as G
+import Data.Maybe ( catMaybes )
import VeriFuzz.Circuit.Base
import VeriFuzz.Circuit.Internal
import VeriFuzz.Verilog.AST
diff --git a/src/VeriFuzz/Circuit/Internal.hs b/src/VeriFuzz/Circuit/Internal.hs
index 3a7346f..5220f4d 100644
--- a/src/VeriFuzz/Circuit/Internal.hs
+++ b/src/VeriFuzz/Circuit/Internal.hs
@@ -19,9 +19,11 @@ module VeriFuzz.Circuit.Internal
)
where
-import Data.Graph.Inductive (Graph, Node)
-import qualified Data.Graph.Inductive as G
-import qualified Data.Text as T
+import Data.Graph.Inductive ( Graph
+ , Node
+ )
+import qualified Data.Graph.Inductive as G
+import qualified Data.Text as T
-- | Convert an integer into a label.
--
diff --git a/src/VeriFuzz/Circuit/Random.hs b/src/VeriFuzz/Circuit/Random.hs
index 58e855c..2750de8 100644
--- a/src/VeriFuzz/Circuit/Random.hs
+++ b/src/VeriFuzz/Circuit/Random.hs
@@ -18,13 +18,14 @@ module VeriFuzz.Circuit.Random
)
where
-import Data.Graph.Inductive (Context)
-import qualified Data.Graph.Inductive as G
-import Data.Graph.Inductive.PatriciaTree (Gr)
-import Data.List (nub)
-import Hedgehog (Gen)
-import qualified Hedgehog.Gen as Hog
-import qualified Hedgehog.Range as Hog
+import Data.Graph.Inductive ( Context )
+import qualified Data.Graph.Inductive as G
+import Data.Graph.Inductive.PatriciaTree
+ ( Gr )
+import Data.List ( nub )
+import Hedgehog ( Gen )
+import qualified Hedgehog.Gen as Hog
+import qualified Hedgehog.Range as Hog
import VeriFuzz.Circuit.Base
dupFolder :: (Eq a, Eq b) => Context a b -> [Context a b] -> [Context a b]
diff --git a/src/VeriFuzz/Config.hs b/src/VeriFuzz/Config.hs
index 19cdd68..0fc9435 100644
--- a/src/VeriFuzz/Config.hs
+++ b/src/VeriFuzz/Config.hs
@@ -77,18 +77,22 @@ module VeriFuzz.Config
)
where
-import Control.Applicative (Alternative)
-import Control.Lens hiding ((.=))
-import Data.List.NonEmpty (NonEmpty (..))
-import Data.Maybe (fromMaybe)
-import Data.Text (Text, pack)
-import qualified Data.Text.IO as T
-import Data.Version (showVersion)
+import Control.Applicative ( Alternative )
+import Control.Lens hiding ( (.=) )
+import Data.List.NonEmpty ( NonEmpty(..) )
+import Data.Maybe ( fromMaybe )
+import Data.Text ( Text
+ , pack
+ )
+import qualified Data.Text.IO as T
+import Data.Version ( showVersion )
import Development.GitRev
-import Hedgehog.Internal.Seed (Seed)
-import Paths_verifuzz (version)
-import Shelly (toTextIgnore)
-import Toml (TomlCodec, (.=))
+import Hedgehog.Internal.Seed ( Seed )
+import Paths_verifuzz ( version )
+import Shelly ( toTextIgnore )
+import Toml ( TomlCodec
+ , (.=)
+ )
import qualified Toml
import VeriFuzz.Sim.Quartus
import VeriFuzz.Sim.Vivado
diff --git a/src/VeriFuzz/Fuzz.hs b/src/VeriFuzz/Fuzz.hs
index fcc96d3..dd7fe7b 100644
--- a/src/VeriFuzz/Fuzz.hs
+++ b/src/VeriFuzz/Fuzz.hs
@@ -27,33 +27,40 @@ module VeriFuzz.Fuzz
)
where
-import Control.DeepSeq (force)
-import Control.Exception.Lifted (finally)
-import Control.Lens hiding ((<.>))
-import Control.Monad (forM, replicateM)
+import Control.DeepSeq ( force )
+import Control.Exception.Lifted ( finally )
+import Control.Lens hiding ( (<.>) )
+import Control.Monad ( forM
+ , replicateM
+ )
import Control.Monad.IO.Class
-import Control.Monad.Trans.Class (lift)
-import Control.Monad.Trans.Control (MonadBaseControl)
-import Control.Monad.Trans.Maybe (runMaybeT)
-import Control.Monad.Trans.Reader hiding (local)
+import Control.Monad.Trans.Class ( lift )
+import Control.Monad.Trans.Control ( MonadBaseControl )
+import Control.Monad.Trans.Maybe ( runMaybeT )
+import Control.Monad.Trans.Reader
+ hiding ( local )
import Control.Monad.Trans.State.Strict
-import qualified Crypto.Random.DRBG as C
-import Data.ByteString (ByteString)
-import Data.List (nubBy, sort)
-import Data.Maybe (isNothing)
-import Data.Text (Text)
-import qualified Data.Text as T
+import qualified Crypto.Random.DRBG as C
+import Data.ByteString ( ByteString )
+import Data.List ( nubBy
+ , sort
+ )
+import Data.Maybe ( isNothing )
+import Data.Text ( Text )
+import qualified Data.Text as T
import Data.Time
-import Data.Tuple (swap)
-import Hedgehog (Gen)
-import qualified Hedgehog.Internal.Gen as Hog
-import Hedgehog.Internal.Seed (Seed)
-import qualified Hedgehog.Internal.Seed as Hog
-import qualified Hedgehog.Internal.Tree as Hog
-import Prelude hiding (FilePath)
-import Shelly hiding (get)
-import Shelly.Lifted (MonadSh, liftSh)
-import System.FilePath.Posix (takeBaseName)
+import Data.Tuple ( swap )
+import Hedgehog ( Gen )
+import qualified Hedgehog.Internal.Gen as Hog
+import Hedgehog.Internal.Seed ( Seed )
+import qualified Hedgehog.Internal.Seed as Hog
+import qualified Hedgehog.Internal.Tree as Hog
+import Prelude hiding ( FilePath )
+import Shelly hiding ( get )
+import Shelly.Lifted ( MonadSh
+ , liftSh
+ )
+import System.FilePath.Posix ( takeBaseName )
import VeriFuzz.Config
import VeriFuzz.Internal
import VeriFuzz.Reduce
@@ -144,7 +151,7 @@ failedSynthesis :: MonadSh m => Fuzz m [SynthTool]
failedSynthesis = fmap toSynth . filter failed . _fuzzSynthStatus <$> get
where
failed (SynthStatus _ (Fail SynthFail) _) = True
- failed _ = False
+ failed _ = False
toSynth (SynthStatus s _ _) = s
make :: MonadSh m => FilePath -> m ()
@@ -216,27 +223,24 @@ equivalence src = do
simulation :: (MonadIO m, MonadSh m) => SourceInfo -> Fuzz m ()
simulation src = do
- synth <- passEquiv
- vals <- liftIO $ generateByteString 20
+ synth <- passEquiv
+ vals <- liftIO $ generateByteString 20
+ ident <- liftSh $ equiv vals defaultIdentitySynth
resTimes <- liftSh $ mapM (equiv vals) $ conv <$> synth
- liftSh $ inspect resTimes
+ liftSh
+ . inspect
+ $ (\(_, r) -> bimap show (T.unpack . T.take 10 . showBS) r)
+ <$> (ident : resTimes)
where
- conv (SynthResult a _ _ _) = a
- equiv b a =
- toolRun ("simulation for " <> toText a)
- . runResultT
- $ do
- make dir
- pop dir $ do
- liftSh $ do
- cp
- ( fromText ".."
- </> fromText (toText a)
- </> synthOutput a
- )
- $ synthOutput a
- writefile "rtl.v" $ genSource src
- runSimIc defaultIcarus a src b
+ conv (SynthResult _ a _ _) = a
+ equiv b a = toolRun ("simulation for " <> toText a) . runResultT $ do
+ make dir
+ pop dir $ do
+ liftSh $ do
+ cp (fromText ".." </> fromText (toText a) </> synthOutput a)
+ $ synthOutput a
+ writefile "rtl.v" $ genSource src
+ runSimIc defaultIcarus a src b
where dir = fromText $ "simulation_" <> toText a
-- | Generate a specific number of random bytestrings of size 256.
@@ -257,7 +261,7 @@ failEquivWithIdentity = filter withIdentity . _fuzzSynthResults <$> get
where
withIdentity (SynthResult (IdentitySynth _) _ (Fail EquivFail) _) = True
withIdentity (SynthResult _ (IdentitySynth _) (Fail EquivFail) _) = True
- withIdentity _ = False
+ withIdentity _ = False
passEquiv :: (MonadSh m) => Fuzz m [SynthResult]
passEquiv = filter withIdentity . _fuzzSynthResults <$> get
@@ -367,7 +371,7 @@ fuzz gen conf = do
?~ seed'
(tsynth, _) <- titleRun "Synthesis" $ synthesis src
(tequiv, _) <- titleRun "Equivalence Check" $ equivalence src
- (_, _) <- titleRun "Simulation" $ simulation src
+ (_ , _) <- titleRun "Simulation" $ simulation src
fails <- failEquivWithIdentity
synthFails <- failedSynthesis
redResult <-
diff --git a/src/VeriFuzz/Internal.hs b/src/VeriFuzz/Internal.hs
index fd9d409..b5ce3ba 100644
--- a/src/VeriFuzz/Internal.hs
+++ b/src/VeriFuzz/Internal.hs
@@ -20,12 +20,14 @@ module VeriFuzz.Internal
)
where
-import Data.ByteString (ByteString)
-import Data.ByteString.Builder (byteStringHex, toLazyByteString)
-import qualified Data.ByteString.Lazy as L
-import Data.Text (Text)
-import qualified Data.Text as T
-import Data.Text.Encoding (decodeUtf8)
+import Data.ByteString ( ByteString )
+import Data.ByteString.Builder ( byteStringHex
+ , toLazyByteString
+ )
+import qualified Data.ByteString.Lazy as L
+import Data.Text ( Text )
+import qualified Data.Text as T
+import Data.Text.Encoding ( decodeUtf8 )
-- | Function to show a bytestring in a hex format.
showBS :: ByteString -> Text
diff --git a/src/VeriFuzz/Reduce.hs b/src/VeriFuzz/Reduce.hs
index 7cee31c..6bae371 100644
--- a/src/VeriFuzz/Reduce.hs
+++ b/src/VeriFuzz/Reduce.hs
@@ -35,18 +35,22 @@ module VeriFuzz.Reduce
)
where
-import Control.Lens hiding ((<.>))
-import Control.Monad (void)
-import Control.Monad.IO.Class (MonadIO, liftIO)
-import Data.Foldable (foldrM)
-import Data.List (nub)
-import Data.List.NonEmpty (NonEmpty (..))
-import qualified Data.List.NonEmpty as NonEmpty
-import Data.Maybe (mapMaybe)
-import Data.Text (Text)
-import Shelly ((<.>))
+import Control.Lens hiding ( (<.>) )
+import Control.Monad ( void )
+import Control.Monad.IO.Class ( MonadIO
+ , liftIO
+ )
+import Data.Foldable ( foldrM )
+import Data.List ( nub )
+import Data.List.NonEmpty ( NonEmpty(..) )
+import qualified Data.List.NonEmpty as NonEmpty
+import Data.Maybe ( mapMaybe )
+import Data.Text ( Text )
+import Shelly ( (<.>) )
import qualified Shelly
-import Shelly.Lifted (MonadSh, liftSh)
+import Shelly.Lifted ( MonadSh
+ , liftSh
+ )
import VeriFuzz.Internal
import VeriFuzz.Result
import VeriFuzz.Sim
diff --git a/src/VeriFuzz/Report.hs b/src/VeriFuzz/Report.hs
index a3c4ebd..3037b34 100644
--- a/src/VeriFuzz/Report.hs
+++ b/src/VeriFuzz/Report.hs
@@ -41,23 +41,33 @@ module VeriFuzz.Report
)
where
-import Control.DeepSeq (NFData, rnf)
-import Control.Lens hiding (Identity, (<.>))
-import Data.Bifunctor (bimap)
-import Data.ByteString (ByteString)
-import Data.Maybe (fromMaybe)
-import Data.Monoid (Endo)
-import Data.Text (Text)
+import Control.DeepSeq ( NFData
+ , rnf
+ )
+import Control.Lens hiding ( Identity
+ , (<.>)
+ )
+import Data.Bifunctor ( bimap )
+import Data.ByteString ( ByteString )
+import Data.Maybe ( fromMaybe )
+import Data.Monoid ( Endo )
+import Data.Text ( Text )
import qualified Data.Text as T
-import Data.Text.Lazy (toStrict)
+import Data.Text.Lazy ( toStrict )
import Data.Time
-import Data.Vector (fromList)
-import Prelude hiding (FilePath)
-import Shelly (FilePath, fromText,
- toTextIgnore, (<.>), (</>))
-import Statistics.Sample (meanVariance)
-import Text.Blaze.Html (Html, (!))
-import Text.Blaze.Html.Renderer.Text (renderHtml)
+import Data.Vector ( fromList )
+import Prelude hiding ( FilePath )
+import Shelly ( FilePath
+ , fromText
+ , toTextIgnore
+ , (<.>)
+ , (</>)
+ )
+import Statistics.Sample ( meanVariance )
+import Text.Blaze.Html ( Html
+ , (!)
+ )
+import Text.Blaze.Html.Renderer.Text ( renderHtml )
import qualified Text.Blaze.Html5 as H
import qualified Text.Blaze.Html5.Attributes as A
import VeriFuzz.Config
diff --git a/src/VeriFuzz/Result.hs b/src/VeriFuzz/Result.hs
index c02690f..4ea7988 100644
--- a/src/VeriFuzz/Result.hs
+++ b/src/VeriFuzz/Result.hs
@@ -31,9 +31,14 @@ import Control.Monad.Base
import Control.Monad.IO.Class
import Control.Monad.Trans.Class
import Control.Monad.Trans.Control
-import Data.Bifunctor (Bifunctor (..))
-import Shelly (RunFailed (..), Sh, catch_sh)
-import Shelly.Lifted (MonadSh, liftSh)
+import Data.Bifunctor ( Bifunctor(..) )
+import Shelly ( RunFailed(..)
+ , Sh
+ , catch_sh
+ )
+import Shelly.Lifted ( MonadSh
+ , liftSh
+ )
-- | Result type which is equivalent to 'Either' or 'Error'. This is
-- reimplemented so that there is full control over the 'Monad' definition and
diff --git a/src/VeriFuzz/Sim/Icarus.hs b/src/VeriFuzz/Sim/Icarus.hs
index 7f90814..8e62136 100644
--- a/src/VeriFuzz/Sim/Icarus.hs
+++ b/src/VeriFuzz/Sim/Icarus.hs
@@ -17,28 +17,35 @@ module VeriFuzz.Sim.Icarus
)
where
-import Control.DeepSeq (NFData, rnf, rwhnf)
+import Control.DeepSeq ( NFData
+ , rnf
+ , rwhnf
+ )
import Control.Lens
-import Control.Monad (void)
-import Crypto.Hash (Digest, hash)
-import Crypto.Hash.Algorithms (SHA256)
-import Data.Binary (encode)
+import Control.Monad ( void )
+import Crypto.Hash ( Digest
+ , hash
+ )
+import Crypto.Hash.Algorithms ( SHA256 )
+import Data.Binary ( encode )
import Data.Bits
-import qualified Data.ByteArray as BA (convert)
-import Data.ByteString (ByteString)
-import qualified Data.ByteString as B
-import Data.ByteString.Lazy (toStrict)
-import qualified Data.ByteString.Lazy as L (ByteString)
-import Data.Char (digitToInt)
-import Data.Foldable (fold)
-import Data.List (transpose)
-import Data.Maybe (listToMaybe)
-import Data.Text (Text)
-import qualified Data.Text as T
-import Numeric (readInt)
-import Prelude hiding (FilePath)
+import qualified Data.ByteArray as BA
+ ( convert )
+import Data.ByteString ( ByteString )
+import qualified Data.ByteString as B
+import Data.ByteString.Lazy ( toStrict )
+import qualified Data.ByteString.Lazy as L
+ ( ByteString )
+import Data.Char ( digitToInt )
+import Data.Foldable ( fold )
+import Data.List ( transpose )
+import Data.Maybe ( listToMaybe )
+import Data.Text ( Text )
+import qualified Data.Text as T
+import Numeric ( readInt )
+import Prelude hiding ( FilePath )
import Shelly
-import Shelly.Lifted (liftSh)
+import Shelly.Lifted ( liftSh )
import VeriFuzz.Sim.Internal
import VeriFuzz.Sim.Template
import VeriFuzz.Verilog.AST
@@ -129,37 +136,60 @@ runSimIcarusWithFile sim f _ = annotate SimFail . liftSh $ do
(runFoldLines (mempty :: ByteString) callback (vvpPath sim) ["main"])
fromBytes :: ByteString -> Integer
-fromBytes = B.foldl' f 0
- where
- f a b = a `shiftL` 8 .|. fromIntegral b
+fromBytes = B.foldl' f 0 where f a b = a `shiftL` 8 .|. fromIntegral b
runSimIc
- :: (Synthesiser b) => Icarus -> b -> SourceInfo -> [ByteString] -> ResultSh ByteString
+ :: (Synthesiser b)
+ => Icarus
+ -> b
+ -> SourceInfo
+ -> [ByteString]
+ -> ResultSh ByteString
runSimIc sim1 synth1 srcInfo bss = do
dir <- liftSh pwd
- let top = srcInfo ^. mainModule
+ let top = srcInfo ^. mainModule
let inConcat = (RegConcat (Id . fromPort <$> (top ^. modInPorts)))
- let tb = instantiateMod top $ ModDecl
- "testbench"
- []
- []
- [ Initial
- $ fold [ BlockAssign (Assign "clk" Nothing 0)
- , BlockAssign (Assign inConcat Nothing 0)
- ]
- <> fold ((\r -> TimeCtrl 10 (Just $ BlockAssign (Assign inConcat Nothing r)))
- . fromInteger . fromBytes <$> bss)
- <> (SysTaskEnable $ Task "finish" [])
- , Always . TimeCtrl 5 . Just $ BlockAssign (Assign "clk" Nothing (UnOp UnNot (Id "clk")))
- , Always . EventCtrl (EPosEdge "clk") . Just . SysTaskEnable $ Task "strobe" ["%b", Id "y"]
- ]
- []
+ let
+ tb = instantiateMod top $ ModDecl
+ "testbench"
+ []
+ []
+ [ Initial
+ $ fold
+ [ BlockAssign (Assign "clk" Nothing 0)
+ , BlockAssign (Assign inConcat Nothing 0)
+ ]
+ <> fold
+ ( (\r -> TimeCtrl
+ 10
+ (Just $ BlockAssign (Assign inConcat Nothing r))
+ )
+ . fromInteger
+ . fromBytes
+ <$> bss
+ )
+ <> (SysTaskEnable $ Task "finish" [])
+ , Always . TimeCtrl 5 . Just $ BlockAssign
+ (Assign "clk" Nothing (UnOp UnNot (Id "clk")))
+ , Always . EventCtrl (EPosEdge "clk") . Just . SysTaskEnable $ Task
+ "strobe"
+ ["%b", Id "y"]
+ ]
+ []
liftSh . writefile "testbench.v" $ icarusTestbench (Verilog [tb]) synth1
liftSh $ exe dir "icarus" "iverilog" ["-o", "main", "testbench.v"]
- liftSh $ B.take 8 . BA.convert . (hash :: ByteString -> Digest SHA256) <$> logCommand
- dir
- "vvp"
- (runFoldLines (mempty :: ByteString) callback (vvpPath sim1) ["main"])
+ liftSh
+ $ B.take 8
+ . BA.convert
+ . (hash :: ByteString -> Digest SHA256)
+ <$> logCommand
+ dir
+ "vvp"
+ (runFoldLines (mempty :: ByteString)
+ callback
+ (vvpPath sim1)
+ ["main"]
+ )
where
exe dir name e = void . errExit False . logCommand dir name . timeout e
diff --git a/src/VeriFuzz/Sim/Identity.hs b/src/VeriFuzz/Sim/Identity.hs
index bfded0b..95b4097 100644
--- a/src/VeriFuzz/Sim/Identity.hs
+++ b/src/VeriFuzz/Sim/Identity.hs
@@ -16,11 +16,16 @@ module VeriFuzz.Sim.Identity
)
where
-import Control.DeepSeq (NFData, rnf, rwhnf)
-import Data.Text (Text, unpack)
-import Prelude hiding (FilePath)
-import Shelly (FilePath)
-import Shelly.Lifted (writefile)
+import Control.DeepSeq ( NFData
+ , rnf
+ , rwhnf
+ )
+import Data.Text ( Text
+ , unpack
+ )
+import Prelude hiding ( FilePath )
+import Shelly ( FilePath )
+import Shelly.Lifted ( writefile )
import VeriFuzz.Sim.Internal
import VeriFuzz.Verilog.AST
import VeriFuzz.Verilog.CodeGen
diff --git a/src/VeriFuzz/Sim/Internal.hs b/src/VeriFuzz/Sim/Internal.hs
index d35ad86..a05a96f 100644
--- a/src/VeriFuzz/Sim/Internal.hs
+++ b/src/VeriFuzz/Sim/Internal.hs
@@ -40,20 +40,26 @@ module VeriFuzz.Sim.Internal
where
import Control.Lens
-import Control.Monad (forM, void)
-import Control.Monad.Catch (throwM)
-import Data.Bits (shiftL)
-import Data.ByteString (ByteString)
-import qualified Data.ByteString as B
-import Data.Maybe (catMaybes)
-import Data.Text (Text)
-import qualified Data.Text as T
-import Data.Time.Format (defaultTimeLocale, formatTime)
-import Data.Time.LocalTime (getZonedTime)
-import Prelude hiding (FilePath)
+import Control.Monad ( forM
+ , void
+ )
+import Control.Monad.Catch ( throwM )
+import Data.Bits ( shiftL )
+import Data.ByteString ( ByteString )
+import qualified Data.ByteString as B
+import Data.Maybe ( catMaybes )
+import Data.Text ( Text )
+import qualified Data.Text as T
+import Data.Time.Format ( defaultTimeLocale
+ , formatTime
+ )
+import Data.Time.LocalTime ( getZonedTime )
+import Prelude hiding ( FilePath )
import Shelly
-import Shelly.Lifted (MonadSh, liftSh)
-import System.FilePath.Posix (takeBaseName)
+import Shelly.Lifted ( MonadSh
+ , liftSh
+ )
+import System.FilePath.Posix ( takeBaseName )
import VeriFuzz.Internal
import VeriFuzz.Result
import VeriFuzz.Verilog.AST
diff --git a/src/VeriFuzz/Sim/Quartus.hs b/src/VeriFuzz/Sim/Quartus.hs
index 4217abb..e0fbba5 100644
--- a/src/VeriFuzz/Sim/Quartus.hs
+++ b/src/VeriFuzz/Sim/Quartus.hs
@@ -16,11 +16,16 @@ module VeriFuzz.Sim.Quartus
)
where
-import Control.DeepSeq (NFData, rnf, rwhnf)
-import Data.Text (Text, unpack)
-import Prelude hiding (FilePath)
+import Control.DeepSeq ( NFData
+ , rnf
+ , rwhnf
+ )
+import Data.Text ( Text
+ , unpack
+ )
+import Prelude hiding ( FilePath )
import Shelly
-import Shelly.Lifted (liftSh)
+import Shelly.Lifted ( liftSh )
import VeriFuzz.Sim.Internal
import VeriFuzz.Verilog.AST
import VeriFuzz.Verilog.CodeGen
diff --git a/src/VeriFuzz/Sim/Vivado.hs b/src/VeriFuzz/Sim/Vivado.hs
index a4feb07..8697a0f 100644
--- a/src/VeriFuzz/Sim/Vivado.hs
+++ b/src/VeriFuzz/Sim/Vivado.hs
@@ -16,11 +16,16 @@ module VeriFuzz.Sim.Vivado
)
where
-import Control.DeepSeq (NFData, rnf, rwhnf)
-import Data.Text (Text, unpack)
-import Prelude hiding (FilePath)
+import Control.DeepSeq ( NFData
+ , rnf
+ , rwhnf
+ )
+import Data.Text ( Text
+ , unpack
+ )
+import Prelude hiding ( FilePath )
import Shelly
-import Shelly.Lifted (liftSh)
+import Shelly.Lifted ( liftSh )
import VeriFuzz.Sim.Internal
import VeriFuzz.Sim.Template
import VeriFuzz.Verilog.AST
diff --git a/src/VeriFuzz/Sim/XST.hs b/src/VeriFuzz/Sim/XST.hs
index 71a4e1b..f5faae5 100644
--- a/src/VeriFuzz/Sim/XST.hs
+++ b/src/VeriFuzz/Sim/XST.hs
@@ -18,12 +18,17 @@ module VeriFuzz.Sim.XST
)
where
-import Control.DeepSeq (NFData, rnf, rwhnf)
-import Data.Text (Text, unpack)
-import Prelude hiding (FilePath)
+import Control.DeepSeq ( NFData
+ , rnf
+ , rwhnf
+ )
+import Data.Text ( Text
+ , unpack
+ )
+import Prelude hiding ( FilePath )
import Shelly
-import Shelly.Lifted (liftSh)
-import Text.Shakespeare.Text (st)
+import Shelly.Lifted ( liftSh )
+import Text.Shakespeare.Text ( st )
import VeriFuzz.Sim.Internal
import VeriFuzz.Sim.Template
import VeriFuzz.Verilog.AST
diff --git a/src/VeriFuzz/Sim/Yosys.hs b/src/VeriFuzz/Sim/Yosys.hs
index 02a00d5..8f9d4a7 100644
--- a/src/VeriFuzz/Sim/Yosys.hs
+++ b/src/VeriFuzz/Sim/Yosys.hs
@@ -20,14 +20,19 @@ module VeriFuzz.Sim.Yosys
)
where
-import Control.DeepSeq (NFData, rnf, rwhnf)
+import Control.DeepSeq ( NFData
+ , rnf
+ , rwhnf
+ )
import Control.Lens
-import Control.Monad (void)
-import Data.Text (Text, unpack)
-import Prelude hiding (FilePath)
+import Control.Monad ( void )
+import Data.Text ( Text
+ , unpack
+ )
+import Prelude hiding ( FilePath )
import Shelly
-import Shelly.Lifted (liftSh)
-import Text.Shakespeare.Text (st)
+import Shelly.Lifted ( liftSh )
+import Text.Shakespeare.Text ( st )
import VeriFuzz.Result
import VeriFuzz.Sim.Internal
import VeriFuzz.Sim.Template
diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs
index f201064..43063e6 100644
--- a/src/VeriFuzz/Verilog/AST.hs
+++ b/src/VeriFuzz/Verilog/AST.hs
@@ -139,14 +139,18 @@ module VeriFuzz.Verilog.AST
)
where
-import Control.Lens hiding ((<|))
+import Control.Lens hiding ( (<|) )
import Data.Data
import Data.Data.Lens
-import Data.Functor.Foldable.TH (makeBaseFunctor)
-import Data.List.NonEmpty (NonEmpty (..), (<|))
-import Data.String (IsString, fromString)
-import Data.Text (Text)
-import Data.Traversable (sequenceA)
+import Data.Functor.Foldable.TH ( makeBaseFunctor )
+import Data.List.NonEmpty ( NonEmpty(..)
+ , (<|)
+ )
+import Data.String ( IsString
+ , fromString
+ )
+import Data.Text ( Text )
+import Data.Traversable ( sequenceA )
import VeriFuzz.Verilog.BitVec
-- | Identifier in Verilog. This is just a string of characters that can either
diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs
index 6ef1959..82945aa 100644
--- a/src/VeriFuzz/Verilog/CodeGen.hs
+++ b/src/VeriFuzz/Verilog/CodeGen.hs
@@ -22,13 +22,15 @@ module VeriFuzz.Verilog.CodeGen
)
where
-import Data.Data (Data)
-import Data.List.NonEmpty (NonEmpty (..), toList)
-import Data.Text (Text)
-import qualified Data.Text as T
+import Data.Data ( Data )
+import Data.List.NonEmpty ( NonEmpty(..)
+ , toList
+ )
+import Data.Text ( Text )
+import qualified Data.Text as T
import Data.Text.Prettyprint.Doc
-import Numeric (showHex)
-import VeriFuzz.Internal hiding (comma)
+import Numeric ( showHex )
+import VeriFuzz.Internal hiding ( comma )
import VeriFuzz.Verilog.AST
import VeriFuzz.Verilog.BitVec
diff --git a/src/VeriFuzz/Verilog/Eval.hs b/src/VeriFuzz/Verilog/Eval.hs
index 4a43c19..d8840e3 100644
--- a/src/VeriFuzz/Verilog/Eval.hs
+++ b/src/VeriFuzz/Verilog/Eval.hs
@@ -17,9 +17,9 @@ module VeriFuzz.Verilog.Eval
where
import Data.Bits
-import Data.Foldable (fold)
-import Data.Functor.Foldable hiding (fold)
-import Data.Maybe (listToMaybe)
+import Data.Foldable ( fold )
+import Data.Functor.Foldable hiding ( fold )
+import Data.Maybe ( listToMaybe )
import VeriFuzz.Verilog.AST
import VeriFuzz.Verilog.BitVec
diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs
index e52a158..0a6ece5 100644
--- a/src/VeriFuzz/Verilog/Gen.hs
+++ b/src/VeriFuzz/Verilog/Gen.hs
@@ -22,17 +22,18 @@ module VeriFuzz.Verilog.Gen
)
where
-import Control.Lens hiding (Context)
-import Control.Monad (replicateM)
-import Control.Monad.Trans.Class (lift)
-import Control.Monad.Trans.Reader hiding (local)
+import Control.Lens hiding ( Context )
+import Control.Monad ( replicateM )
+import Control.Monad.Trans.Class ( lift )
+import Control.Monad.Trans.Reader
+ hiding ( local )
import Control.Monad.Trans.State.Strict
-import Data.Foldable (fold)
-import Data.Functor.Foldable (cata)
-import qualified Data.Text as T
-import Hedgehog (Gen)
-import qualified Hedgehog.Gen as Hog
-import qualified Hedgehog.Range as Hog
+import Data.Foldable ( fold )
+import Data.Functor.Foldable ( cata )
+import qualified Data.Text as T
+import Hedgehog ( Gen )
+import qualified Hedgehog.Gen as Hog
+import qualified Hedgehog.Range as Hog
import VeriFuzz.Config
import VeriFuzz.Internal
import VeriFuzz.Verilog.AST
diff --git a/src/VeriFuzz/Verilog/Internal.hs b/src/VeriFuzz/Verilog/Internal.hs
index 8d19c14..16148cf 100644
--- a/src/VeriFuzz/Verilog/Internal.hs
+++ b/src/VeriFuzz/Verilog/Internal.hs
@@ -29,7 +29,7 @@ module VeriFuzz.Verilog.Internal
where
import Control.Lens
-import Data.Text (Text)
+import Data.Text ( Text )
import VeriFuzz.Verilog.AST
regDecl :: Identifier -> ModItem
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs
index 0fb4c49..e4a10df 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Verilog/Mutate.hs
@@ -41,10 +41,12 @@ module VeriFuzz.Verilog.Mutate
where
import Control.Lens
-import Data.Foldable (fold)
-import Data.Maybe (catMaybes, fromMaybe)
-import Data.Text (Text)
-import qualified Data.Text as T
+import Data.Foldable ( fold )
+import Data.Maybe ( catMaybes
+ , fromMaybe
+ )
+import Data.Text ( Text )
+import qualified Data.Text as T
import VeriFuzz.Circuit.Internal
import VeriFuzz.Internal
import VeriFuzz.Verilog.AST
@@ -337,30 +339,30 @@ declareMod ports = initMod . (modItems %~ (decl ++))
-- >>> GenVerilog . simplify $ (Id "y") + (Id "x")
-- (y + x)
simplify :: Expr -> Expr
-simplify (BinOp (Number (BitVec _ 1)) BinAnd e) = e
-simplify (BinOp e BinAnd (Number (BitVec _ 1))) = e
-simplify (BinOp (Number (BitVec _ 0)) BinAnd _) = Number 0
-simplify (BinOp _ BinAnd (Number (BitVec _ 0))) = Number 0
-simplify (BinOp e BinPlus (Number (BitVec _ 0))) = e
-simplify (BinOp (Number (BitVec _ 0)) BinPlus e) = e
+simplify (BinOp (Number (BitVec _ 1)) BinAnd e) = e
+simplify (BinOp e BinAnd (Number (BitVec _ 1))) = e
+simplify (BinOp (Number (BitVec _ 0)) BinAnd _) = Number 0
+simplify (BinOp _ BinAnd (Number (BitVec _ 0))) = Number 0
+simplify (BinOp e BinPlus (Number (BitVec _ 0))) = e
+simplify (BinOp (Number (BitVec _ 0)) BinPlus e) = e
simplify (BinOp e BinMinus (Number (BitVec _ 0))) = e
simplify (BinOp (Number (BitVec _ 0)) BinMinus e) = e
simplify (BinOp e BinTimes (Number (BitVec _ 1))) = e
simplify (BinOp (Number (BitVec _ 1)) BinTimes e) = e
simplify (BinOp _ BinTimes (Number (BitVec _ 0))) = Number 0
simplify (BinOp (Number (BitVec _ 0)) BinTimes _) = Number 0
-simplify (BinOp e BinOr (Number (BitVec _ 0))) = e
-simplify (BinOp (Number (BitVec _ 0)) BinOr e) = e
-simplify (BinOp e BinLSL (Number (BitVec _ 0))) = e
-simplify (BinOp (Number (BitVec _ 0)) BinLSL e) = e
-simplify (BinOp e BinLSR (Number (BitVec _ 0))) = e
-simplify (BinOp (Number (BitVec _ 0)) BinLSR e) = e
-simplify (BinOp e BinASL (Number (BitVec _ 0))) = e
-simplify (BinOp (Number (BitVec _ 0)) BinASL e) = e
-simplify (BinOp e BinASR (Number (BitVec _ 0))) = e
-simplify (BinOp (Number (BitVec _ 0)) BinASR e) = e
-simplify (UnOp UnPlus e) = e
-simplify e = e
+simplify (BinOp e BinOr (Number (BitVec _ 0))) = e
+simplify (BinOp (Number (BitVec _ 0)) BinOr e) = e
+simplify (BinOp e BinLSL (Number (BitVec _ 0))) = e
+simplify (BinOp (Number (BitVec _ 0)) BinLSL e) = e
+simplify (BinOp e BinLSR (Number (BitVec _ 0))) = e
+simplify (BinOp (Number (BitVec _ 0)) BinLSR e) = e
+simplify (BinOp e BinASL (Number (BitVec _ 0))) = e
+simplify (BinOp (Number (BitVec _ 0)) BinASL e) = e
+simplify (BinOp e BinASR (Number (BitVec _ 0))) = e
+simplify (BinOp (Number (BitVec _ 0)) BinASR e) = e
+simplify (UnOp UnPlus e) = e
+simplify e = e
-- | Remove all 'Identifier' that do not appeare in the input list from an
-- 'Expr'. The identifier will be replaced by @1'b0@, which can then later be
diff --git a/src/VeriFuzz/Verilog/Parser.hs b/src/VeriFuzz/Verilog/Parser.hs
index 68d0ef3..0820e48 100644
--- a/src/VeriFuzz/Verilog/Parser.hs
+++ b/src/VeriFuzz/Verilog/Parser.hs
@@ -26,17 +26,20 @@ module VeriFuzz.Verilog.Parser
where
import Control.Lens
-import Control.Monad (void)
-import Data.Bifunctor (bimap)
+import Control.Monad ( void )
+import Data.Bifunctor ( bimap )
import Data.Bits
-import Data.Functor (($>))
-import Data.Functor.Identity (Identity)
-import Data.List (isInfixOf, isPrefixOf, null)
-import Data.List.NonEmpty (NonEmpty (..))
-import Data.Text (Text)
-import qualified Data.Text as T
-import qualified Data.Text.IO as T
-import Text.Parsec hiding (satisfy)
+import Data.Functor ( ($>) )
+import Data.Functor.Identity ( Identity )
+import Data.List ( isInfixOf
+ , isPrefixOf
+ , null
+ )
+import Data.List.NonEmpty ( NonEmpty(..) )
+import Data.Text ( Text )
+import qualified Data.Text as T
+import qualified Data.Text.IO as T
+import Text.Parsec hiding ( satisfy )
import Text.Parsec.Expr
import VeriFuzz.Internal
import VeriFuzz.Verilog.AST
diff --git a/src/VeriFuzz/Verilog/Quote.hs b/src/VeriFuzz/Verilog/Quote.hs
index 362cf06..f0b7c96 100644
--- a/src/VeriFuzz/Verilog/Quote.hs
+++ b/src/VeriFuzz/Verilog/Quote.hs
@@ -18,8 +18,8 @@ module VeriFuzz.Verilog.Quote
where
import Data.Data
-import qualified Data.Text as T
-import qualified Language.Haskell.TH as TH
+import qualified Data.Text as T
+import qualified Language.Haskell.TH as TH
import Language.Haskell.TH.Quote
import Language.Haskell.TH.Syntax
import VeriFuzz.Verilog.Parser
diff --git a/test/Doctest.hs b/test/Doctest.hs
index 7463dfe..9dc22a4 100644
--- a/test/Doctest.hs
+++ b/test/Doctest.hs
@@ -1,7 +1,10 @@
module Main where
-import Build_doctests (flags, module_sources, pkgs)
-import Test.DocTest (doctest)
+import Build_doctests ( flags
+ , module_sources
+ , pkgs
+ )
+import Test.DocTest ( doctest )
main :: IO ()
main = doctest args where args = flags ++ pkgs ++ module_sources
diff --git a/test/Parser.hs b/test/Parser.hs
index 03cc3a6..84f1906 100644
--- a/test/Parser.hs
+++ b/test/Parser.hs
@@ -17,10 +17,15 @@ module Parser
where
import Control.Lens
-import Data.Either (either, isRight)
-import Hedgehog (Gen, Property, (===))
-import qualified Hedgehog as Hog
-import qualified Hedgehog.Gen as Hog
+import Data.Either ( either
+ , isRight
+ )
+import Hedgehog ( Gen
+ , Property
+ , (===)
+ )
+import qualified Hedgehog as Hog
+import qualified Hedgehog.Gen as Hog
import Test.Tasty
import Test.Tasty.Hedgehog
import Test.Tasty.HUnit
diff --git a/test/Property.hs b/test/Property.hs
index 001c7d3..4e17695 100644
--- a/test/Property.hs
+++ b/test/Property.hs
@@ -11,16 +11,23 @@ module Property
)
where
-import Data.Either (either, isRight)
-import qualified Data.Graph.Inductive as G
-import Data.Text (Text)
-import Hedgehog (Gen, Property, (===))
-import qualified Hedgehog as Hog
-import Hedgehog.Function (Arg, Vary)
-import qualified Hedgehog.Function as Hog
-import qualified Hedgehog.Gen as Hog
-import qualified Hedgehog.Range as Hog
-import Parser (parserTests)
+import Data.Either ( either
+ , isRight
+ )
+import qualified Data.Graph.Inductive as G
+import Data.Text ( Text )
+import Hedgehog ( Gen
+ , Property
+ , (===)
+ )
+import qualified Hedgehog as Hog
+import Hedgehog.Function ( Arg
+ , Vary
+ )
+import qualified Hedgehog.Function as Hog
+import qualified Hedgehog.Gen as Hog
+import qualified Hedgehog.Range as Hog
+import Parser ( parserTests )
import Test.Tasty
import Test.Tasty.Hedgehog
import Text.Parsec
diff --git a/test/Reduce.hs b/test/Reduce.hs
index be5ead3..bc47d94 100644
--- a/test/Reduce.hs
+++ b/test/Reduce.hs
@@ -17,7 +17,7 @@ module Reduce
)
where
-import Data.List ((\\))
+import Data.List ( (\\) )
import Test.Tasty
import Test.Tasty.HUnit
import VeriFuzz
diff --git a/test/Unit.hs b/test/Unit.hs
index 84508c4..aaffe09 100644
--- a/test/Unit.hs
+++ b/test/Unit.hs
@@ -4,9 +4,9 @@ module Unit
where
import Control.Lens
-import Data.List.NonEmpty (NonEmpty (..))
-import Parser (parseUnitTests)
-import Reduce (reduceUnitTests)
+import Data.List.NonEmpty ( NonEmpty(..) )
+import Parser ( parseUnitTests )
+import Reduce ( reduceUnitTests )
import Test.Tasty
import Test.Tasty.HUnit
import VeriFuzz