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| author | Yann Herklotz <git@yannherklotz.com> | 2019-08-01 01:38:47 +0200 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-08-01 01:38:47 +0200 |
| commit | a59af9347e35cb5b7909d05e0d9318e974515497 (patch) | |
| tree | 80ed153bb94fa6fe72be0262b1e9af403b9936f1 | |
| parent | 1aec47ead1c9fb65ab5b5e4b55337a79ff9314af (diff) | |
| download | verismith-a59af9347e35cb5b7909d05e0d9318e974515497.tar.gz verismith-a59af9347e35cb5b7909d05e0d9318e974515497.zip | |
Fix to read the verilog instead of a formal repr
| -rw-r--r-- | src/VeriFuzz/Sim/Yosys.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Sim/Yosys.hs b/src/VeriFuzz/Sim/Yosys.hs index d69bc69..8c73b86 100644 --- a/src/VeriFuzz/Sim/Yosys.hs +++ b/src/VeriFuzz/Sim/Yosys.hs @@ -73,7 +73,7 @@ runSynthYosys sim (SourceInfo _ src) = do "yosys" (yosysPath sim) [ "-p" - , "read -formal " <> inp <> "; synth; write_verilog -noattr " <> out + , "read_verilog " <> inp <> "; synth; write_verilog -noattr " <> out ] where inpf = "rtl.v" |