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author | Yann Herklotz <git@yannherklotz.com> | 2019-11-26 14:25:57 +0000 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2019-11-26 14:45:03 +0000 |
commit | 67e676f7bfc03d84025449dc8caa6d8716057a11 (patch) | |
tree | 50baf89ca82fe940a05bfb796337cd8e87a72e99 | |
parent | 834f4278d54748bca715e9471cf7a4520868b6f5 (diff) | |
download | verismith-67e676f7bfc03d84025449dc8caa6d8716057a11.tar.gz verismith-67e676f7bfc03d84025449dc8caa6d8716057a11.zip |
Add new yosys report
-rw-r--r-- | bugs/yosys_13.md | 80 |
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diff --git a/bugs/yosys_13.md b/bugs/yosys_13.md new file mode 100644 index 0000000..64bc3c0 --- /dev/null +++ b/bugs/yosys_13.md @@ -0,0 +1,80 @@ +# Assignment of 0 to for loop variable leads to a 1 in MSB + +[ Not fixed | [Issue 1531](https://github.com/YosysHQ/yosys/issues/1531) ] + +## Affected versions + +- Yosys 0.8 +- Yosys 0.9 +- Yosys [`0466c48`](https://github.com/YosysHQ/yosys/commit/0466c48533ad2831a95c6b63c3a190adb76499e9) + +## Description + +In the following Verilog code, the expected output is that `y` should always be assigned the value of `w`, as the for loop only executes once, meaning the MSB in `i` should never be set. Even though only one bit is assigned, it should be zero extended to the size of the `i` reg. + +```verilog +module top (y, clk, w); + output reg y = 1'b0; + input clk, w; + reg [1:0] i = 2'b00; + always @(posedge clk) + // If the constant below is set to 2'b00, the correct output is generated. + // vvvv + for (i = 1'b0; i < 2'b01; i = i + 2'b01) + y <= w || i[1:1]; +endmodule +``` + +### Steps to reproduce the issue + +To reproduce, copy the Verilog code above into a file named `top.v` and synthesise it using the following command: + +``` shell +yosys -q -p "read_verilog top.v; synth; write_verilog syn.v" +``` + +`syn.v` will then contain an assignment of `1'b1` to `y` instead of an assignment of `w` to `y`. + +This was reproduced with the following versions of Yosys: + +- 0.8 +- 0.9 +- [`0466c48`](https://github.com/YosysHQ/yosys/commit/0466c48533ad2831a95c6b63c3a190adb76499e9) + +### Expected behavior + +The expected output is an assignment of `w` to `y`, which is achieved when the assignment in the loop is set to 2 bits instead of 1. + +``` verilog +/* Generated by Yosys 0.9+932 (git sha1 0466c485, clang 9.0.0 -fPIC -Os) */ + +module top(y, clk, w); + input clk; + wire [1:0] i; + input w; + output y; + reg y = 1'h0; + always @(posedge clk) + y <= w; + assign i = 2'h0; +endmodule +``` + +### Actual behavior + +However, with the Verilog above, the actual output of Yosys is: + +``` verilog +/* Generated by Yosys 0.9+932 (git sha1 0466c485, clang 9.0.0 -fPIC -Os) */ + +module top(y, clk, w); + input clk; + wire [1:0] i; + input w; + output y; + reg y = 1'h0; + always @(posedge clk) + y <= 1'h1; // 1'h1 instead of expected w. + assign i = 2'h0; +endmodule +``` |