| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Upgrading packages to work with 8.2.2feature/update-dependencies | Yann Herklotz | 2020-03-06 | 2 | -13/+13 |
| * | Fix spacing in the generated Verilog | Yann Herklotz | 2020-03-03 | 1 | -16/+20 |
| * | Add case statement to the AST | Yann Herklotz | 2020-03-03 | 2 | -1/+41 |
| * | Add contact information | Yann Herklotz | 2020-02-28 | 1 | -0/+3 |
| * | Update adding info for commercial license | Yann Herklotz | 2020-02-28 | 2 | -1/+9 |
| * | Add bib entry to readme and update results | Yann Herklotz | 2020-02-23 | 1 | -6/+26 |
| * | Update license notices | Yann Herklotz | 2020-01-06 | 38 | -38/+38 |
| * | Bump version | Yann Herklotz | 2020-01-06 | 1 | -2/+2 |
| * | Update license to dual license GPLv3 | Yann Herklotz | 2020-01-06 | 40 | -68/+720 |
| * | More changes to instructions | Yann Herklotz | 2020-01-01 | 2 | -21/+21 |
| * | Fix to the instructions | Yann Herklotz | 2020-01-01 | 2 | -21/+21 |
| * | Update instructions | Yann Herklotz | 2020-01-01 | 2 | -19/+49 |
| * | Update instructions | Yann Herklotz | 2020-01-01 | 2 | -10/+271 |
| * | Add instructions | Yann Herklotz | 2019-12-26 | 2 | -16/+168 |
| * | Update | Yann Herklotz | 2019-12-26 | 2 | -10/+123 |
| * | Update instructions further | Yann Herklotz | 2019-12-26 | 2 | -4/+47 |
| * | Update instructions | Yann Herklotz | 2019-12-26 | 2 | -9/+7 |
| * | Add instructions | Yann Herklotz | 2019-12-26 | 1 | -0/+27 |
| * | Add some instructions | Yann Herklotz | 2019-12-26 | 1 | -0/+15 |
| * | Bump version to v0.6.0.2v0.6.0.2 | Yann Herklotz | 2019-12-26 | 1 | -2/+2 |
| * | Add correct cleaning function back | Yann Herklotz | 2019-12-26 | 1 | -1/+1 |
| * | Bump version to v0.6.0.1v0.6.0.1 | Yann Herklotz | 2019-12-26 | 1 | -2/+2 |
| * | Add configuration for default Yosys location | Yann Herklotz | 2019-12-26 | 3 | -7/+28 |
| * | Update documentation | Yann Herklotz | 2019-12-26 | 1 | -26/+49 |
| * | Add reduction stage back | Yann Herklotz | 2019-12-26 | 1 | -0/+1 |
| * | Bump to version 0.6.0.0v0.6.0.0 | Yann Herklotz | 2019-12-25 | 1 | -2/+2 |
| * | Add synthesis tools | Yann Herklotz | 2019-12-19 | 1 | -0/+3 |
| * | Add links | Yann Herklotz | 2019-12-19 | 1 | -4/+4 |
| * | Add external dependencies to README | Yann Herklotz | 2019-12-19 | 1 | -2/+7 |
| * | Add new Yosys report | Yann Herklotz | 2019-12-13 | 2 | -0/+16 |
| * | Add quartuslight | Yann Herklotz | 2019-12-10 | 1 | -2/+2 |
| * | Do not run counter example if no rerunner is specified | Yann Herklotz | 2019-12-03 | 7 | -26/+40 |
| * | Set aigsmt to none | Yann Herklotz | 2019-12-03 | 1 | -1/+1 |
| * | More minimisation | Yann Herklotz | 2019-12-03 | 2 | -3/+11 |
| * | Move to resourcesv0.5.0.1fpga20 | Yann Herklotz | 2019-11-26 | 1 | -6/+10 |
| * | Add more information in README | Yann Herklotz | 2019-11-26 | 1 | -2/+2 |
| * | Update link to paper | Yann Herklotz | 2019-11-26 | 1 | -1/+1 |
| * | Update links in the readme | Yann Herklotz | 2019-11-26 | 1 | -1/+6 |
| * | Add new yosys report | Yann Herklotz | 2019-11-26 | 1 | -0/+80 |
| * | Add different identifier for forloops | Yann Herklotz | 2019-11-24 | 1 | -15/+17 |
| * | Upgrade version to v0.5.0.0v0.5.0.0 | Yann Herklotz | 2019-11-24 | 1 | -2/+2 |
| * | Add ModConnNamed in testbench | Yann Herklotz | 2019-11-24 | 1 | -1/+1 |
| * | Add extension to simulation reduction | Yann Herklotz | 2019-11-24 | 1 | -1/+1 |
| * | Fix more changes to for loops | Yann Herklotz | 2019-11-24 | 1 | -1/+1 |
| * | Do not mutate the expression in the for loop | Yann Herklotz | 2019-11-24 | 1 | -1/+1 |
| * | Fix build | Yann Herklotz | 2019-11-24 | 1 | -1/+1 |
| * | Add output of v file during reduction | Yann Herklotz | 2019-11-24 | 2 | -35/+20 |
| * | Show the result as it is run | Yann Herklotz | 2019-11-24 | 1 | -4/+4 |
| * | Add cross-check between netlists | Yann Herklotz | 2019-11-24 | 3 | -11/+16 |
| * | Merge branch 'master' of github.com:ymherklotz/verismith | Yann Herklotz | 2019-11-24 | 2 | -2/+2 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
| aboutsummaryrefslogtreecommitdiffstats |