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| author | Yann Herklotz <git@yannherklotz.com> | 2019-12-10 02:25:08 +0000 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-12-10 02:25:22 +0000 |
| commit | b94f2528d898d6965d5fcf23a38a7df0dda7f538 (patch) | |
| tree | 7093c07e68195b85752118d889cd39b09abd99a0 | |
| parent | d29813263852c866f20f88504860120820499411 (diff) | |
| download | verismith-b94f2528d898d6965d5fcf23a38a7df0dda7f538.tar.gz verismith-b94f2528d898d6965d5fcf23a38a7df0dda7f538.zip | |
Add quartuslight
| -rw-r--r-- | src/Verismith/Tool/QuartusLight.hs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/Verismith/Tool/QuartusLight.hs b/src/Verismith/Tool/QuartusLight.hs index 86c9a3a..17f8570 100644 --- a/src/Verismith/Tool/QuartusLight.hs +++ b/src/Verismith/Tool/QuartusLight.hs @@ -59,8 +59,8 @@ runSynthQuartusLight sim (SourceInfo top src) = do , "s/^module/(* multstyle = \"logic\" *) module/;" , toTextIgnore inpf ] - writefile quartusSdc $ "create_clock -period 5 -name clk [get_ports clock]" - writefile quartusTcl $ quartusSynthConfig sim quartusSdc top inpf + writefile quartusSdc "create_clock -period 5 -name clk [get_ports clock]" + writefile quartusTcl $ quartusLightSynthConfig sim quartusSdc top inpf ex (exec "quartus_sh") ["-t", toTextIgnore quartusTcl] liftSh $ do cp (fromText "simulation/vcs" </> fromText top <.> "vo") |