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| author | Yann Herklotz <git@yannherklotz.com> | 2019-12-03 19:41:54 +0000 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-12-03 19:41:54 +0000 |
| commit | c59a9178c701f4a514b980d0b8d66a6bd238fb19 (patch) | |
| tree | dc66b94dc1a9c10946ea976b59de55cf91e13913 | |
| parent | c6ee6729e637590627779ddc5c1a46b865eb6bd4 (diff) | |
| download | verismith-c59a9178c701f4a514b980d0b8d66a6bd238fb19.tar.gz verismith-c59a9178c701f4a514b980d0b8d66a6bd238fb19.zip | |
Set aigsmt to none
| -rw-r--r-- | src/Verismith/Tool/Template.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/Verismith/Tool/Template.hs b/src/Verismith/Tool/Template.hs index 3bd5a2d..0b63e91 100644 --- a/src/Verismith/Tool/Template.hs +++ b/src/Verismith/Tool/Template.hs @@ -140,7 +140,7 @@ sbyConfig :: (Synthesiser a, Synthesiser b) => FilePath -> a -> b -> SourceInfo sbyConfig datadir sim1 sim2 (SourceInfo top _) = [st|[options] multiclock on mode prove -aigsmt z3 +aigsmt none [engines] abc pdr |