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| author | Yann Herklotz <git@yannherklotz.com> | 2019-10-25 09:05:31 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-10-25 09:05:31 +0100 |
| commit | 2b461deaf32e065a71d83235f3c5648eea93fb19 (patch) | |
| tree | 9be4c4e311cfbd1f4775671ce897b2aa5d2cf662 | |
| parent | 85a017f3d4c8cc3efb876e0864da8d6a033f88dc (diff) | |
| download | verismith-2b461deaf32e065a71d83235f3c5648eea93fb19.tar.gz verismith-2b461deaf32e065a71d83235f3c5648eea93fb19.zip | |
Fix subtle issue with module generation
| -rw-r--r-- | src/Verismith/Generate.hs | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/Verismith/Generate.hs b/src/Verismith/Generate.hs index a896c3e..25b9306 100644 --- a/src/Verismith/Generate.hs +++ b/src/Verismith/Generate.hs @@ -445,6 +445,7 @@ instantiate (ModDecl i outP inP _ _) = do context <- lget outs <- replicateM (length outP) (nextPort Wire) ins <- take (length inpFixed) <$> Hog.shuffle (context ^. variables) + insLit <- replicateM (length inpFixed - length ins) (Number <$> genBitVec) mapM_ (uncurry process) . zip (ins ^.. traverse . portName) $ inpFixed ^.. traverse . portSize ident <- makeIdentifier "modinst" vs <- view variables <$> lget |