| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Remove DRBG from Fuzz.hsfix/remove-DRBG | Yann Herklotz | 2019-11-05 | 1 | -13/+17 |
| * | Remove DRBG dependency | Yann Herklotz | 2019-11-05 | 2 | -27/+32 |
| * | Add Vagrant file | Yann Herklotz Grave | 2019-11-05 | 1 | -0/+74 |
| * | Classify Verilog correctly | Yann Herklotz | 2019-11-05 | 1 | -1/+2 |
| * | Update reducer script | Yann Herklotz | 2019-11-05 | 1 | -8/+22 |
| * | Add reduction pass to remove constants from concat | Yann Herklotz | 2019-11-05 | 5 | -15/+88 |
| * | Add asynchronous load | Yann Herklotz | 2019-11-05 | 1 | -2/+6 |
| * | Add support for Quartus using projects | Yann Herklotz | 2019-11-04 | 2 | -17/+45 |
| * | Fix testsuite by adding preprocessor | Yann Herklotz | 2019-11-01 | 1 | -10/+9 |
| * | Fix dffeas specification | Yann Herklotz | 2019-10-31 | 1 | -4/+2 |
| * | Add parsing of existing rtl when starting fuzz run | Yann Herklotz | 2019-10-31 | 2 | -10/+31 |
| * | Add reducer testing script | Yann Herklotz | 2019-10-31 | 1 | -0/+51 |
| * | Add data-file installation path | Yann Herklotz | 2019-10-29 | 7 | -40/+58 |
| * | Revert .envrc code | Yann Herklotz | 2019-10-28 | 1 | -83/+0 |
| * | Run simulation on all tools passing synthesis | Yann Herklotz | 2019-10-28 | 1 | -20/+27 |
| * | Add --no-reduction | Yann Herklotz | 2019-10-28 | 2 | -23/+20 |
| * | Add mtl dependency to enable easier use of transformers | Yann Herklotz | 2019-10-27 | 3 | -172/+202 |
| * | Add OptParser to separate option parsing | Yann Herklotz | 2019-10-27 | 2 | -245/+270 |
| * | Update configv0.4.0.1 | Yann Herklotz | 2019-10-25 | 1 | -2/+4 |
| * | Update the version string for future release | Yann Herklotz | 2019-10-25 | 1 | -1/+1 |
| * | Change to one line | Yann Herklotz | 2019-10-25 | 1 | -61/+17 |
| * | Add comment to code generation | Yann Herklotz | 2019-10-25 | 1 | -1/+1 |
| * | Update README with current build procedure | Yann Herklotz | 2019-10-25 | 1 | -11/+29 |
| * | Add the literal list to the mod instantiation | Yann Herklotz | 2019-10-25 | 1 | -2/+3 |
| * | Fix subtle issue with module generation | Yann Herklotz | 2019-10-25 | 1 | -0/+1 |
| * | Change location of the html reports | Yann Herklotz | 2019-10-18 | 2 | -4/+6 |
| * | Add -k functionality | Yann Herklotz | 2019-10-18 | 3 | -9/+31 |
| * | Edit .envrc for nix | Yann Herklotz | 2019-10-18 | 1 | -1/+1 |
| * | Rename Sim to Tool | Yann Herklotz | 2019-10-18 | 15 | -77/+72 |
| * | Update default configuration | Yann Herklotz | 2019-10-18 | 1 | -13/+10 |
| * | Update runner | Yann Herklotz | 2019-10-18 | 1 | -15/+22 |
| * | Remove reference to nix files | Yann Herklotz | 2019-10-07 | 1 | -1/+0 |
| * | Clean up default.nix file | Yann Herklotz | 2019-10-07 | 1 | -5/+3 |
| * | Remove nix folder | Yann Herklotz | 2019-10-07 | 4 | -77/+0 |
| * | Fix cabal filev0.4.0.0 | Yann Herklotz | 2019-10-06 | 1 | -1/+10 |
| * | Pin the nix repository | Yann Herklotz | 2019-10-06 | 1 | -3/+13 |
| * | Fix spelling in readme | Yann Herklotz | 2019-10-06 | 1 | -3/+3 |
| * | Change benchmark information | Yann Herklotz | 2019-10-06 | 1 | -15/+16 |
| * | Test cases pass again | Yann Herklotz | 2019-10-06 | 1 | -12/+0 |
| * | [Fix #63] Make build pass again | Yann Herklotz | 2019-10-06 | 5 | -113/+59 |
| * | Add more scripts | Yann Herklotz | 2019-09-18 | 4 | -0/+190 |
| * | Rename main modules | Yann Herklotz | 2019-09-18 | 43 | -259/+275 |
| * | Small changes to .cabal | Yann Herklotz | 2019-09-06 | 1 | -2/+7 |
| * | Rename cabal file to fix nix | Yann Herklotz | 2019-09-04 | 1 | -0/+0 |
| * | Renaming to VeriSmith | Yann Herklotz | 2019-09-04 | 34 | -0/+0 |
| * | Change name from VeriFuzz to VeriSmith | Yann Herklotz | 2019-08-29 | 46 | -379/+372 |
| * | Add new bug that was found | Yann Herklotz | 2019-08-15 | 1 | -0/+1 |
| * | Added benchmark results for comparison | Yann Herklotz | 2019-08-07 | 1 | -0/+27 |
| * | Update aws setup script | Yann Herklotz | 2019-08-07 | 1 | -2/+3 |
| * | Fix wording of readme | Yann Herklotz | 2019-08-01 | 1 | -3/+4 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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