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| author | Yann Herklotz <ymherklotz@gmail.com> | 2018-11-09 21:43:19 +0000 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-11-09 21:43:19 +0000 |
| commit | 7d68a1e7ec557e62615a7f9eea438cff7805b120 (patch) | |
| tree | c9761f8e6241daf5bfe15069c7de245dddaff2ee | |
| parent | e5a7cfbaeaac6a5f9ca9a7cd9883cf788417681a (diff) | |
| download | verismith-7d68a1e7ec557e62615a7f9eea438cff7805b120.tar.gz verismith-7d68a1e7ec557e62615a7f9eea438cff7805b120.zip | |
Add testbench to the end
| -rw-r--r-- | src/Test/VeriFuzz/CodeGen.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/Test/VeriFuzz/CodeGen.hs b/src/Test/VeriFuzz/CodeGen.hs index 6cf2d27..80f813e 100644 --- a/src/Test/VeriFuzz/CodeGen.hs +++ b/src/Test/VeriFuzz/CodeGen.hs @@ -22,7 +22,7 @@ generate graph = <> ");\n" <> fromList (imap " input wire " ";\n" inp) <> fromList (imap " output wire " ";\n" out) - <> "endmodule\n" + <> "endmodule\n\nmodule main;\n initial\n begin\n $display(\"Hello, world\");\n $finish;\n end\nendmodule" where and a b c = a == b && a /= c inputs n = indeg graph n == 0 && outdeg graph n /= 0 |