Add Bit vector instead of using numbers

6 files changed, 142 insertions, 184 deletions

diff --git a/src/VeriFuzz/Verilog.hs b/src/VeriFuzz/Verilog.hs
index 4d3b82c..dda3da1 100644
--- a/src/VeriFuzz/Verilog.hs
+++ b/src/VeriFuzz/Verilog.hs
@@ -18,14 +18,11 @@ module VeriFuzz.Verilog
     , randomMod
     , GenVerilog(..)
     , genSource
-    , getVerilog
     -- * Primitives
     -- ** Identifier
     , Identifier(..)
-    , getIdentifier
     -- ** Control
     , Delay(..)
-    , getDelay
     , Event(..)
     -- ** Operators
     , BinaryOperator(..)
@@ -40,8 +37,7 @@ module VeriFuzz.Verilog
     , regExprId
     , regExpr
     , regSizeId
-    , regSizeMSB
-    , regSizeLSB
+    , regSizeRange
     , regConc
     -- ** Ports
     , PortDir(..)
@@ -53,24 +49,8 @@ module VeriFuzz.Verilog
     , portName
     -- * Expression
     , Expr(..)
-    , exprSize
-    , exprVal
-    , exprId
-    , exprConcat
-    , exprUnOp
-    , exprPrim
-    , exprLhs
-    , exprBinOp
-    , exprRhs
-    , exprCond
-    , exprTrue
-    , exprFalse
-    , exprFunc
-    , exprBody
-    , exprStr
     , ConstExpr(..)
     , constNum
-    , Function(..)
     -- * Assignment
     , Assign(..)
     , assignReg
diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs
index 3a8d14a..2030bc7 100644
--- a/src/VeriFuzz/Verilog/CodeGen.hs
+++ b/src/VeriFuzz/Verilog/CodeGen.hs
@@ -21,16 +21,16 @@ module VeriFuzz.Verilog.CodeGen
     )
 where
 
-import           Control.Lens          (view, (^.))
-import           Data.Foldable         (fold)
-import           Data.List.NonEmpty    (NonEmpty (..), toList)
-import           Data.Text             (Text)
-import qualified Data.Text             as T
-import qualified Data.Text.IO          as T
-import           Numeric               (showHex)
+import           Data.Foldable           (fold)
+import           Data.List.NonEmpty      (NonEmpty (..), toList)
+import           Data.Text               (Text)
+import qualified Data.Text               as T
+import qualified Data.Text.IO            as T
+import           Numeric                 (showHex)
 import           VeriFuzz.Internal
 import           VeriFuzz.Sim.Internal
 import           VeriFuzz.Verilog.AST
+import           VeriFuzz.Verilog.BitVec
 
 -- | 'Source' class which determines that source code is able to be generated
 -- from the data structure using 'genSource'. This will be stored in 'Text' and
@@ -87,16 +87,18 @@ identifier (Identifier i) = i
 -- | Conversts 'Port' to 'Text' for the module list, which means it only
 -- generates a list of identifiers.
 modPort :: Port -> Text
-modPort p = p ^. portName . getIdentifier
+modPort (Port _ _ _ (Identifier i)) = i
 
 -- | Generate the 'Port' description.
 port :: Port -> Text
-port (Port tp sgn low sz (Identifier name)) = t <> sign <> size <> name
+port (Port tp sgn r (Identifier name)) = t <> sign <> range r <> name
   where
-    t = flip mappend " " $ pType tp
-    size = "[" <> showT (low+sz-1) <> ":" <> showT low <> "] "
+    t    = flip mappend " " $ pType tp
     sign = signed sgn
 
+range :: Range -> Text
+range (Range msb lsb) = "[" <> constExpr msb <> ":" <> constExpr lsb <> "] "
+
 signed :: Bool -> Text
 signed True = "signed "
 signed _    = ""
@@ -124,39 +126,34 @@ moduleItem (LocalParamDecl p) = localParamList p <> ";\n"
 
 mConn :: ModConn -> Text
 mConn (ModConn c       ) = expr c
-mConn (ModConnNamed n c) = "." <> n ^. getIdentifier <> "(" <> expr c <> ")"
+mConn (ModConnNamed n c) = "." <> getIdentifier n <> "(" <> expr c <> ")"
 
 -- | Generate continuous assignment
 contAssign :: ContAssign -> Text
 contAssign (ContAssign val e) =
-    "assign " <> val ^. getIdentifier <> " = " <> expr e <> ";\n"
-
--- | Generate 'Function' to 'Text'
-func :: Function -> Text
-func SignedFunc   = "$signed"
-func UnsignedFunc = "$unsigned"
+    "assign " <> getIdentifier val <> " = " <> expr e <> ";\n"
 
 -- | Generate 'Expr' to 'Text'.
 expr :: Expr -> Text
 expr (BinOp eRhs bin eLhs) =
     "(" <> expr eRhs <> binaryOp bin <> expr eLhs <> ")"
-expr (Number s n) = showNum s n
-expr (Id     i  ) = i ^. getIdentifier
-expr (Concat c  ) = "{" <> comma (expr <$> c) <> "}"
-expr (UnOp u e  ) = "(" <> unaryOp u <> expr e <> ")"
+expr (Number b             ) = showNum b
+expr (Id     i             ) = getIdentifier i
+expr (Concat c             ) = "{" <> comma (expr <$> c) <> "}"
+expr (UnOp u e             ) = "(" <> unaryOp u <> expr e <> ")"
 expr (Cond l t f) = "(" <> expr l <> " ? " <> expr t <> " : " <> expr f <> ")"
-expr (Func f e  ) = func f <> "(" <> expr e <> ")"
-expr (Str t     ) = "\"" <> t <> "\""
+expr (Appl (Identifier f) e) = f <> "(" <> expr e <> ")"
+expr (Str t                ) = "\"" <> t <> "\""
 
-showNum :: Int -> Integer -> Text
-showNum s n =
+showNum :: BitVec -> Text
+showNum (BitVec s n) =
     "(" <> minus <> showT s <> "'h" <> T.pack (showHex (abs n) "") <> ")"
   where
     minus | signum n >= 0 = ""
           | otherwise     = "-"
 
 constExpr :: ConstExpr -> Text
-constExpr (ConstNum s n ) = showNum s n
+constExpr (ConstNum    b) = showNum b
 constExpr (ParamId     i) = identifier i
 constExpr (ConstConcat c) = "{" <> comma (constExpr <$> c) <> "}"
 constExpr (ConstUnOp u e) = "(" <> unaryOp u <> constExpr e <> ")"
@@ -210,11 +207,11 @@ unaryOp UnNxorInv = "^~"
 
 -- | Generate verilog code for an 'Event'.
 event :: Event -> Text
-event (EId   i)    = "@(" <> i ^. getIdentifier <> ")"
+event (EId   i)    = "@(" <> getIdentifier i <> ")"
 event (EExpr e)    = "@(" <> expr e <> ")"
 event EAll         = "@*"
-event (EPosEdge i) = "@(posedge " <> i ^. getIdentifier <> ")"
-event (ENegEdge i) = "@(negedge " <> i ^. getIdentifier <> ")"
+event (EPosEdge i) = "@(posedge " <> getIdentifier i <> ")"
+event (ENegEdge i) = "@(negedge " <> getIdentifier i <> ")"
 
 -- | Generates verilog code for a 'Delay'.
 delay :: Delay -> Text
@@ -222,10 +219,9 @@ delay (Delay i) = "#" <> showT i
 
 -- | Generate the verilog code for an 'LVal'.
 lVal :: LVal -> Text
-lVal (RegId i    ) = i ^. getIdentifier
-lVal (RegExpr i e) = i ^. getIdentifier <> " [" <> expr e <> "]"
-lVal (RegSize i msb lsb) =
-    i ^. getIdentifier <> " [" <> constExpr msb <> ":" <> constExpr lsb <> "]"
+lVal (RegId i    ) = getIdentifier i
+lVal (RegExpr i e) = getIdentifier i <> " [" <> expr e <> "]"
+lVal (RegSize i r) = getIdentifier i <> " " <> range r
 lVal (RegConcat e) = "{" <> comma (expr <$> e) <> "}"
 
 pType :: PortType -> Text
@@ -257,9 +253,8 @@ statement (ForLoop a e incr stmnt) =
         <> statement stmnt
 
 task :: Task -> Text
-task (Task name e) | null e    = i
-                   | otherwise = i <> "(" <> comma (expr <$> e) <> ")"
-    where i = name ^. getIdentifier
+task (Task (Identifier i) e) | null e    = i
+                             | otherwise = i <> "(" <> comma (expr <$> e) <> ")"
 
 -- | Render the 'Text' to 'IO'. This is equivalent to 'putStrLn'.
 render :: (Source a) => a -> IO ()
@@ -268,7 +263,7 @@ render = T.putStrLn . genSource
 -- Instances
 
 instance Source Identifier where
-    genSource = view getIdentifier
+    genSource = getIdentifier
 
 instance Source Task where
     genSource = task
diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs
index c325f66..78e278e 100644
--- a/src/VeriFuzz/Verilog/Gen.hs
+++ b/src/VeriFuzz/Verilog/Gen.hs
@@ -34,6 +34,7 @@ import qualified Hedgehog.Range                 as Hog
 import           VeriFuzz.Config
 import           VeriFuzz.Internal
 import           VeriFuzz.Verilog.AST
+import           VeriFuzz.Verilog.BitVec
 import           VeriFuzz.Verilog.Internal
 import           VeriFuzz.Verilog.Mutate
 
@@ -54,10 +55,10 @@ toId = Identifier . ("w" <>) . T.pack . show
 
 toPort :: Identifier -> Gen Port
 toPort ident = do
-    i <- Hog.int $ Hog.linear 1 100
+    i <- range
     return $ wire i ident
 
-sumSize :: [Port] -> Int
+sumSize :: [Port] -> Range
 sumSize ps = sum $ ps ^.. traverse . portSize
 
 random :: [Identifier] -> (Expr -> ContAssign) -> Gen ModItem
@@ -105,62 +106,66 @@ largeNum = Hog.int Hog.linearBounded
 wireSize :: Gen Int
 wireSize = Hog.int $ Hog.linear 2 200
 
+range :: Gen Range
+range = Range <$> fmap fromIntegral wireSize <*> pure 0
+
+genBitVec :: Gen BitVec
+genBitVec = BitVec <$> wireSize <*> fmap fromIntegral largeNum
+
 binOp :: Gen BinaryOperator
-binOp =
-    Hog.element
-        [ BinPlus
-        , BinMinus
-        , BinTimes
+binOp = Hog.element
+    [ BinPlus
+    , BinMinus
+    , BinTimes
         -- , BinDiv
         -- , BinMod
-        , BinEq
-        , BinNEq
+    , BinEq
+    , BinNEq
         -- , BinCEq
         -- , BinCNEq
-        , BinLAnd
-        , BinLOr
-        , BinLT
-        , BinLEq
-        , BinGT
-        , BinGEq
-        , BinAnd
-        , BinOr
-        , BinXor
-        , BinXNor
-        , BinXNorInv
+    , BinLAnd
+    , BinLOr
+    , BinLT
+    , BinLEq
+    , BinGT
+    , BinGEq
+    , BinAnd
+    , BinOr
+    , BinXor
+    , BinXNor
+    , BinXNorInv
         -- , BinPower
-        , BinLSL
-        , BinLSR
-        , BinASL
-        , BinASR
-        ]
+    , BinLSL
+    , BinLSR
+    , BinASL
+    , BinASR
+    ]
 
 unOp :: Gen UnaryOperator
-unOp =
-    Hog.element
-        [ UnPlus
-        , UnMinus
-        , UnNot
-        , UnLNot
-        , UnAnd
-        , UnNand
-        , UnOr
-        , UnNor
-        , UnXor
-        , UnNxor
-        , UnNxorInv
-        ]
+unOp = Hog.element
+    [ UnPlus
+    , UnMinus
+    , UnNot
+    , UnLNot
+    , UnAnd
+    , UnNand
+    , UnOr
+    , UnNor
+    , UnXor
+    , UnNxor
+    , UnNxorInv
+    ]
 
 constExprWithContext :: [Parameter] -> ProbExpr -> Hog.Size -> Gen ConstExpr
 constExprWithContext ps prob size
     | size == 0 = Hog.frequency
-        [ (prob ^. probExprNum, ConstNum <$> wireSize <*> fmap fromIntegral largeNum)
+        [ (prob ^. probExprNum, ConstNum <$> genBitVec)
         , ( if null ps then 0 else prob ^. probExprId
           , ParamId . view paramIdent <$> Hog.element ps
           )
         ]
     | size > 0 = Hog.frequency
-        [ (prob ^. probExprNum, ConstNum <$> wireSize <*> fmap fromIntegral largeNum)
+        [ (prob ^. probExprNum, ConstNum <$> genBitVec)
         , ( if null ps then 0 else prob ^. probExprId
           , ParamId . view paramIdent <$> Hog.element ps
           )
@@ -177,24 +182,18 @@ constExprWithContext ps prob size
     where subexpr y = constExprWithContext ps prob $ size `div` y
 
 exprSafeList :: ProbExpr -> [(Int, Gen Expr)]
-exprSafeList prob =
-    [ ( prob ^. probExprNum
-      , Number <$> wireSize <*> fmap fromIntegral largeNum
-      )
-    ]
+exprSafeList prob = [(prob ^. probExprNum, Number <$> genBitVec)]
 
 exprRecList :: ProbExpr -> (Hog.Size -> Gen Expr) -> [(Int, Gen Expr)]
 exprRecList prob subexpr =
-    [ ( prob ^. probExprNum
-      , Number <$> wireSize <*> fmap fromIntegral largeNum
-      )
+    [ (prob ^. probExprNum     , Number <$> genBitVec)
     , (prob ^. probExprConcat  , Concat <$> listOf1 (subexpr 8))
     , (prob ^. probExprUnOp    , UnOp <$> unOp <*> subexpr 2)
     , (prob ^. probExprStr, Str <$> Hog.text (Hog.linear 0 100) Hog.alphaNum)
     , (prob ^. probExprBinOp   , BinOp <$> subexpr 2 <*> binOp <*> subexpr 2)
     , (prob ^. probExprCond    , Cond <$> subexpr 3 <*> subexpr 3 <*> subexpr 3)
-    , (prob ^. probExprSigned  , Func <$> pure SignedFunc <*> subexpr 2)
-    , (prob ^. probExprUnsigned, Func <$> pure UnsignedFunc <*> subexpr 2)
+    , (prob ^. probExprSigned  , Appl <$> pure "$signed" <*> subexpr 2)
+    , (prob ^. probExprUnsigned, Appl <$> pure "$unsigned" <*> subexpr 2)
     ]
 
 exprWithContext :: ProbExpr -> [Identifier] -> Hog.Size -> Gen Expr
@@ -235,7 +234,7 @@ makeIdentifier prefix = do
 newPort :: PortType -> StateGen Port
 newPort pt = do
     ident <- makeIdentifier . T.toLower $ showT pt
-    p     <- gen $ Port pt <$> Hog.bool <*> pure 0 <*> wireSize <*> pure ident
+    p     <- gen $ Port pt <$> Hog.bool <*> range <*> pure ident
     variables %= (p :)
     return p
 
@@ -256,7 +255,7 @@ contAssign = do
     return $ ContAssign (p ^. portName) expr
 
 lvalFromPort :: Port -> LVal
-lvalFromPort (Port _ _ _ _ i) = RegId i
+lvalFromPort (Port _ _ _ i) = RegId i
 
 probability :: Config -> Probability
 probability c = c ^. configProbability
@@ -296,9 +295,9 @@ conditional = do
 
 forLoop :: StateGen Statement
 forLoop = do
-    num <- Hog.int (Hog.linear 0 20)
-    var     <- lvalFromPort <$> newPort Reg
-    stats   <- seqBlock
+    num   <- Hog.int (Hog.linear 0 20)
+    var   <- lvalFromPort <$> newPort Reg
+    stats <- seqBlock
     return $ ForLoop (Assign var Nothing 0)
                      (BinOp (varId var) BinLT $ fromIntegral num)
                      (Assign var Nothing $ BinOp (varId var) BinPlus 1)
@@ -428,8 +427,8 @@ moduleDef top = do
     context  <- get
     let local = filter (`notElem` portList) $ context ^. variables
     let size  = sum $ local ^.. traverse . portSize
-    let clock = Port Wire False 0 1 "clk"
-    let yport = Port Wire False 0 size "y"
+    let clock = Port Wire False 1 "clk"
+    let yport = Port Wire False size "y"
     let comb  = combineAssigns_ yport local
     declareMod local
         .   ModDecl name [yport] (clock : portList) (mi <> [comb])
diff --git a/src/VeriFuzz/Verilog/Internal.hs b/src/VeriFuzz/Verilog/Internal.hs
index 63072b1..8d19c14 100644
--- a/src/VeriFuzz/Verilog/Internal.hs
+++ b/src/VeriFuzz/Verilog/Internal.hs
@@ -33,10 +33,10 @@ import           Data.Text            (Text)
 import           VeriFuzz.Verilog.AST
 
 regDecl :: Identifier -> ModItem
-regDecl i = Decl Nothing (Port Reg False 0 1 i) Nothing
+regDecl i = Decl Nothing (Port Reg False (Range 1 0) i) Nothing
 
 wireDecl :: Identifier -> ModItem
-wireDecl i = Decl Nothing (Port Wire False 0 1 i) Nothing
+wireDecl i = Decl Nothing (Port Wire False (Range 1 0) i) Nothing
 
 -- | Create an empty module.
 emptyMod :: ModDecl
@@ -51,7 +51,7 @@ addModPort :: Port -> ModDecl -> ModDecl
 addModPort port = modInPorts %~ (:) port
 
 addModDecl :: ModDecl -> Verilog -> Verilog
-addModDecl desc = getVerilog %~ (:) desc
+addModDecl desc = _Wrapped %~ (:) desc
 
 testBench :: ModDecl
 testBench = ModDecl
@@ -65,15 +65,8 @@ testBench = ModDecl
               "and_gate"
               [ModConn $ Id "c", ModConn $ Id "a", ModConn $ Id "b"]
     , Initial $ SeqBlock
-        [ BlockAssign . Assign (RegId "a") Nothing $ Number 1 1
-        , BlockAssign . Assign (RegId "b") Nothing $ Number 1 1
-    -- , TimeCtrl (Delay 1) . Just . SysTaskEnable $ Task "display"
-    --   [ Str "%d & %d = %d"
-    --   , PrimExpr $ PrimId "a"
-    --   , PrimExpr $ PrimId "b"
-    --   , PrimExpr $ PrimId "c"
-    --   ]
-    -- , SysTaskEnable $ Task "finish" []
+        [ BlockAssign . Assign (RegId "a") Nothing $ Number 1
+        , BlockAssign . Assign (RegId "b") Nothing $ Number 1
         ]
     ]
     []
@@ -82,19 +75,19 @@ addTestBench :: Verilog -> Verilog
 addTestBench = addModDecl testBench
 
 defaultPort :: Identifier -> Port
-defaultPort = Port Wire False 0 1
+defaultPort = Port Wire False (Range 1 0)
 
 portToExpr :: Port -> Expr
-portToExpr (Port _ _ _ _ i) = Id i
+portToExpr (Port _ _ _ i) = Id i
 
 modName :: ModDecl -> Text
-modName = view $ modId . getIdentifier
+modName = getIdentifier . view modId
 
 yPort :: Identifier -> Port
-yPort = Port Wire False 0 90
+yPort = Port Wire False (Range 90 0)
 
-wire :: Int -> Identifier -> Port
-wire = Port Wire False 0
+wire :: Range -> Identifier -> Port
+wire = Port Wire False
 
-reg :: Int -> Identifier -> Port
-reg = Port Reg False 0
+reg :: Range -> Identifier -> Port
+reg = Port Reg False
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs
index 536ebef..5fd007d 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Verilog/Mutate.hs
@@ -44,6 +44,7 @@ import qualified Data.Text                 as T
 import           VeriFuzz.Circuit.Internal
 import           VeriFuzz.Internal
 import           VeriFuzz.Verilog.AST
+import           VeriFuzz.Verilog.BitVec
 import           VeriFuzz.Verilog.Internal
 
 -- | Return if the 'Identifier' is in a 'ModDecl'.
@@ -172,10 +173,7 @@ instantiateModSpec_ outChar m = ModInst (m ^. modId) (m ^. modId) conns
 
 filterChar :: Text -> [Identifier] -> [Identifier]
 filterChar t ids =
-    ids
-        &  traverse
-        .  getIdentifier
-        %~ (\x -> fromMaybe x . safe head $ T.splitOn t x)
+    ids & traverse . _Wrapped %~ (\x -> fromMaybe x . safe head $ T.splitOn t x)
 
 -- | Initialise all the inputs and outputs to a module.
 --
@@ -221,8 +219,8 @@ declareMod :: [Port] -> ModDecl -> ModDecl
 declareMod ports = initMod . (modItems %~ (decl ++))
   where
     decl = declf <$> ports
-    declf p@(Port Reg _ _ _ _) = Decl Nothing p (Just 0)
-    declf p                    = Decl Nothing p Nothing
+    declf p@(Port Reg _ _ _) = Decl Nothing p (Just 0)
+    declf p                  = Decl Nothing p Nothing
 
 -- | Simplify an 'Expr' by using constants to remove 'BinaryOperator' and
 -- simplify expressions. To make this work effectively, it should be run until
@@ -234,30 +232,30 @@ declareMod ports = initMod . (modItems %~ (decl ++))
 -- >>> GenVerilog . simplify $ (Id "y") + (Id "x")
 -- (y + x)
 simplify :: Expr -> Expr
-simplify (BinOp (Number _ 1) BinAnd e)   = e
-simplify (BinOp e BinAnd (Number _ 1))   = e
-simplify (BinOp (Number _ 0) BinAnd _)   = Number 1 0
-simplify (BinOp _ BinAnd (Number _ 0))   = Number 1 0
-simplify (BinOp e BinPlus (Number _ 0))  = e
-simplify (BinOp (Number _ 0) BinPlus e)  = e
-simplify (BinOp e BinMinus (Number _ 0)) = e
-simplify (BinOp (Number _ 0) BinMinus e) = e
-simplify (BinOp e BinTimes (Number _ 1)) = e
-simplify (BinOp (Number _ 1) BinTimes e) = e
-simplify (BinOp _ BinTimes (Number _ 0)) = Number 1 0
-simplify (BinOp (Number _ 0) BinTimes _) = Number 1 0
-simplify (BinOp e BinOr (Number _ 0))    = e
-simplify (BinOp (Number _ 0) BinOr e)    = e
-simplify (BinOp e BinLSL (Number _ 0))   = e
-simplify (BinOp (Number _ 0) BinLSL e)   = e
-simplify (BinOp e BinLSR (Number _ 0))   = e
-simplify (BinOp (Number _ 0) BinLSR e)   = e
-simplify (BinOp e BinASL (Number _ 0))   = e
-simplify (BinOp (Number _ 0) BinASL e)   = e
-simplify (BinOp e BinASR (Number _ 0))   = e
-simplify (BinOp (Number _ 0) BinASR e)   = e
-simplify (UnOp UnPlus e)                 = e
-simplify e                               = e
+simplify (BinOp (Number (BitVec _ 1)) BinAnd e)   = e
+simplify (BinOp e BinAnd (Number (BitVec _ 1)))   = e
+simplify (BinOp (Number (BitVec _ 0)) BinAnd _)   = Number 0
+simplify (BinOp _ BinAnd (Number (BitVec _ 0)))   = Number 0
+simplify (BinOp e BinPlus (Number (BitVec _ 0)))  = e
+simplify (BinOp (Number (BitVec _ 0)) BinPlus e)  = e
+simplify (BinOp e BinMinus (Number (BitVec _ 0))) = e
+simplify (BinOp (Number (BitVec _ 0)) BinMinus e) = e
+simplify (BinOp e BinTimes (Number (BitVec _ 1))) = e
+simplify (BinOp (Number (BitVec _ 1)) BinTimes e) = e
+simplify (BinOp _ BinTimes (Number (BitVec _ 0))) = Number 0
+simplify (BinOp (Number (BitVec _ 0)) BinTimes _) = Number 0
+simplify (BinOp e BinOr (Number (BitVec _ 0)))    = e
+simplify (BinOp (Number (BitVec _ 0)) BinOr e)    = e
+simplify (BinOp e BinLSL (Number (BitVec _ 0)))   = e
+simplify (BinOp (Number (BitVec _ 0)) BinLSL e)   = e
+simplify (BinOp e BinLSR (Number (BitVec _ 0)))   = e
+simplify (BinOp (Number (BitVec _ 0)) BinLSR e)   = e
+simplify (BinOp e BinASL (Number (BitVec _ 0)))   = e
+simplify (BinOp (Number (BitVec _ 0)) BinASL e)   = e
+simplify (BinOp e BinASR (Number (BitVec _ 0)))   = e
+simplify (BinOp (Number (BitVec _ 0)) BinASR e)   = e
+simplify (UnOp UnPlus e)                          = e
+simplify e                                        = e
 
 -- | Remove all 'Identifier' that do not appeare in the input list from an
 -- 'Expr'. The identifier will be replaced by @1'b0@, which can then later be
@@ -268,7 +266,7 @@ simplify e                               = e
 removeId :: [Identifier] -> Expr -> Expr
 removeId i = transform trans
   where
-    trans (Id ident) | ident `notElem` i = Number 1 0
+    trans (Id ident) | ident `notElem` i = Number 0
                      | otherwise         = Id ident
     trans e = e
 
diff --git a/src/VeriFuzz/Verilog/Parser.hs b/src/VeriFuzz/Verilog/Parser.hs
index 518bcb9..a7020ec 100644
--- a/src/VeriFuzz/Verilog/Parser.hs
+++ b/src/VeriFuzz/Verilog/Parser.hs
@@ -29,12 +29,12 @@ import qualified Data.Text                   as T
 import           Text.Parsec                 hiding (satisfy)
 import           Text.Parsec.Expr
 import           VeriFuzz.Verilog.AST
+import           VeriFuzz.Verilog.BitVec
 import           VeriFuzz.Verilog.Internal
 import           VeriFuzz.Verilog.Lex
 import           VeriFuzz.Verilog.Preprocess
 import           VeriFuzz.Verilog.Token
 
-
 type Parser = Parsec [Token] ()
 
 type ParseOperator = Operator [Token] () Identity
@@ -87,7 +87,7 @@ parseExpr' :: Parser Expr
 parseExpr' = buildExpressionParser parseTable parseTerm <?> "expr"
 
 decToExpr :: Decimal -> Expr
-decToExpr (Decimal s n) = Number s n
+decToExpr (Decimal s n) = Number $ bitVec s n
 
 -- | Parse a Number depending on if it is in a hex or decimal form. Octal and
 -- binary are not supported yet.
@@ -97,24 +97,17 @@ parseNum = decToExpr <$> number
 parseVar :: Parser Expr
 parseVar = Id <$> identifier
 
-systemFunc :: String -> Parser String
-systemFunc s = satisfy' matchId
+systemFunc :: Parser String
+systemFunc = satisfy' matchId
   where
-    matchId (Token IdSystem s' _) = if s == s' then Just s else Nothing
-    matchId _                     = Nothing
-
-parseFunction :: Parser Function
-parseFunction =
-    systemFunc "$unsigned"
-        $>  UnsignedFunc
-        <|> systemFunc "$signed"
-        $>  SignedFunc
+    matchId (Token IdSystem s _) = Just s
+    matchId _                    = Nothing
 
 parseFun :: Parser Expr
 parseFun = do
-    f    <- parseFunction
+    f    <- systemFunc
     expr <- parens parseExpr
-    return $ Func f expr
+    return $ Appl (Identifier $ T.pack f) expr
 
 parseTerm :: Parser Expr
 parseTerm =
@@ -259,7 +252,7 @@ parseNetDecl pd = do
     range <- option 1 parseRange
     name  <- identifier
     tok' SymSemi
-    return $ Decl pd (Port t sign 0 range name) Nothing
+    return $ Decl pd (Port t sign (fromIntegral range) name) Nothing
     where type_ = tok KWWire $> Wire <|> tok KWReg $> Reg
 
 parsePortDir :: Parser PortDir