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| author | Yann Herklotz <git@ymhg.org> | 2019-11-14 13:41:57 +0000 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-11-14 13:41:57 +0000 |
| commit | 1b0b6315f6194ebdbe0d31aecbc1a125639fd024 (patch) | |
| tree | 96977df68fab8e56e607b44e775c34ec3ff78c03 | |
| parent | e11977ebdf04aff4c9581b6dccec9e7e95f5b2ce (diff) | |
| download | verismith-1b0b6315f6194ebdbe0d31aecbc1a125639fd024.tar.gz verismith-1b0b6315f6194ebdbe0d31aecbc1a125639fd024.zip | |
Add z3 as default equivalence check with ABC
| -rw-r--r-- | src/Verismith/Tool/Template.hs | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/Verismith/Tool/Template.hs b/src/Verismith/Tool/Template.hs index 56a35e5..5402702 100644 --- a/src/Verismith/Tool/Template.hs +++ b/src/Verismith/Tool/Template.hs @@ -120,6 +120,7 @@ sbyConfig :: (Synthesiser a, Synthesiser b) => FilePath -> a -> b -> SourceInfo sbyConfig datadir sim1 sim2 (SourceInfo top _) = [st|[options] multiclock on mode prove +aigsmt z3 [engines] abc pdr |