Add changes to Icarus for fuzzing

6 files changed, 43 insertions, 5 deletions

diff --git a/default.nix b/default.nix
index 516691e..8a896d0 100644
--- a/default.nix
+++ b/default.nix
@@ -1,7 +1,6 @@
 { nixpkgs ? null, compiler ? "ghc865", doBenchmark ? false } :
 let
   pinnedPkg = builtins.fetchGit {
-    name = "nixos-unstable-2020-03-06";
     url = https://github.com/nixos/nixpkgs/;
     rev = "93ba4ecd58602d3f69f74f9d45d60a8f949544e2";
   };
diff --git a/src/Verismith/Tool/Icarus.hs b/src/Verismith/Tool/Icarus.hs
index c020b61..04ec6a4 100644
--- a/src/Verismith/Tool/Icarus.hs
+++ b/src/Verismith/Tool/Icarus.hs
@@ -32,6 +32,7 @@ import qualified Data.ByteString.Lazy as L (ByteString)
 import Data.Char (digitToInt)
 import Data.Foldable (fold)
 import Data.List (transpose)
+import Data.List.NonEmpty (NonEmpty(..), fromList)
 import Data.Maybe (listToMaybe)
 import Data.Text (Text)
 import qualified Data.Text as T
@@ -204,7 +205,7 @@ tbModule' ids bss top =
               BlockAssign
                 (Assign "clk" Nothing (UnOp UnNot (Id "clk"))),
             Always . EventCtrl (EPosEdge "clk") . Just . SysTaskEnable $
-              Task "strobe" ["%b", Id "y"]
+              Task "strobe" ["%b", Concat (fromList $ fmap Id outputs)]
           ]
           []
     ]
@@ -214,6 +215,8 @@ tbModule' ids bss top =
                 . filter (/= (Id "clk"))
                 $ (Id . fromPort <$> (top ^. modInPorts)))
     inIds = RegConcat $ fmap Id ids
+    outputs = top^..modOutPorts.traverse.portName
+
 
 counterTestBench :: CounterEg -> (ModDecl ann) -> (Verilog ann)
 counterTestBench (CounterEg _ states) m = tbModule filtered m
diff --git a/src/Verismith/Verilog/AST.hs b/src/Verismith/Verilog/AST.hs
index d0443e9..cd59094 100644
--- a/src/Verismith/Verilog/AST.hs
+++ b/src/Verismith/Verilog/AST.hs
@@ -66,6 +66,7 @@ module Verismith.Verilog.AST
 
     -- * Expression
     Expr (..),
+    _Id,
     ConstExpr (..),
     ConstExprF (..),
     constToExpr,
@@ -368,6 +369,7 @@ data Expr
   deriving (Eq, Show, Ord, Data, Generic, NFData)
 
 $(makeLenses ''Expr)
+$(makePrisms ''Expr)
 
 $(makeBaseFunctor ''Expr)
 
diff --git a/src/Verismith/Verilog/CodeGen.hs b/src/Verismith/Verilog/CodeGen.hs
index 9a4c12c..7f5dd46 100644
--- a/src/Verismith/Verilog/CodeGen.hs
+++ b/src/Verismith/Verilog/CodeGen.hs
@@ -65,11 +65,11 @@ moduleDecl (ModDeclAnn a m) = sep [hsep ["/*", pretty $ show a, "*/"], moduleDec
 
 -- | Generates a parameter list. Can only be called with a 'NonEmpty' list.
 paramList :: NonEmpty Parameter -> Doc a
-paramList ps = tupled . toList $ parameter <$> ps
+paramList ps = vsep . punctuate ", " . toList $ parameter <$> ps
 
 -- | Generates a localparam list. Can only be called with a 'NonEmpty' list.
 localParamList :: NonEmpty LocalParam -> Doc a
-localParamList ps = tupled . toList $ localParam <$> ps
+localParamList ps = vsep . punctuate ", " . toList $ localParam <$> ps
 
 -- | Generates the assignment for a 'Parameter'.
 parameter :: Parameter -> Doc a
diff --git a/src/Verismith/Verilog/Parser.hs b/src/Verismith/Verilog/Parser.hs
index 80996ba..a10fe22 100644
--- a/src/Verismith/Verilog/Parser.hs
+++ b/src/Verismith/Verilog/Parser.hs
@@ -32,6 +32,7 @@ import Data.Functor (($>))
 import Data.Functor.Identity (Identity)
 import Data.List (isInfixOf, isPrefixOf, null)
 import Data.List.NonEmpty (NonEmpty (..))
+import qualified Data.Map.Strict as Map
 import Data.Text (Text)
 import qualified Data.Text as T
 import qualified Data.Text.IO as T
@@ -521,6 +522,37 @@ parseModDecl = do
       modItem
       paramList
 
+mergeMaybe :: Maybe a -> Maybe a -> Maybe a
+mergeMaybe (Just a) Nothing = Just a
+mergeMaybe Nothing (Just a) = Just a
+mergeMaybe a _ = a
+
+mergeType :: PortType -> PortType -> PortType
+mergeType Reg Wire = Reg
+mergeType Wire Reg = Reg
+mergeType a _ = a
+
+mergePorts :: Port -> Port -> Port
+mergePorts (Port t1 s1 r1 n1) (Port t2 s2 r2 n2) =
+  Port (mergeType t1 t2) (s1 || s2) (if r1 == 0 then r2 else r1) n1
+
+mergeIO :: ModItem a -> ModItem a -> ModItem a
+mergeIO (Decl a1 b1 c1) (Decl a2 b2 c2) = Decl (mergeMaybe a1 a2) (mergePorts b1 b2) (mergeMaybe c1 c2)
+mergeIO a _ = a
+
+genmoditem :: Map.Map Identifier (ModItem a) -> ModItem a -> Map.Map Identifier (ModItem a)
+genmoditem m (Decl a b c) =
+  Map.insertWith mergeIO (b^.portName) (Decl a b c) m
+genmoditem m b = m
+
+modifyelements :: [ModItem a] -> [ModItem a]
+modifyelements ma = ndecl <> nodecl
+  where
+    ndecl = Map.elems $ foldl genmoditem Map.empty ma
+    isDecl Decl{} = True
+    isDecl _ = False
+    nodecl = filter isDecl ma
+
 -- | Parses a 'String' into 'Verilog' by skipping any beginning whitespace
 -- and then parsing multiple Verilog source.
 parseVerilogSrc :: Parser (Verilog ann)
@@ -537,7 +569,7 @@ parseVerilog ::
   -- message if parse fails.
   Either Text (Verilog ann)
 parseVerilog s =
-  bimap showT id
+  bimap showT id --(_Wrapped.traverse.modItems %~ modifyelements)
     . parse parseVerilogSrc (T.unpack s)
     . alexScanTokens
     . preprocess [] (T.unpack s)
diff --git a/verismith.cabal b/verismith.cabal
index d10d28c..e77cf49 100644
--- a/verismith.cabal
+++ b/verismith.cabal
@@ -50,6 +50,7 @@ library
                  , Verismith.Reduce
                  , Verismith.Report
                  , Verismith.Result
+                 , Verismith.Shuffle
                  , Verismith.Tool
                  , Verismith.Tool.Icarus
                  , Verismith.Tool.Identity
@@ -104,6 +105,7 @@ library
                , tomland >=1.0 && <1.3
                , transformers >=0.5 && <0.6
                , transformers-base >=0.4.5 && <0.5
+               , containers
   default-extensions: OverloadedStrings
 
 executable verismith