Change the arguments to Text in the Parser

3 files changed, 31 insertions, 10 deletions

diff --git a/src/VeriFuzz/Verilog/Parser.hs b/src/VeriFuzz/Verilog/Parser.hs
index 383a72e..b7840ff 100644
--- a/src/VeriFuzz/Verilog/Parser.hs
+++ b/src/VeriFuzz/Verilog/Parser.hs
@@ -14,11 +14,13 @@ whole Verilog syntax, as the AST does not support it either.
 module VeriFuzz.Verilog.Parser
     ( -- * Parser
       parseVerilog
-    , parseModDecl
+    , parseVerilogFile
+    , parseSourceInfoFile
     -- ** Internal parsers
     , parseEvent
     , parseStatement
     , parseModItem
+    , parseModDecl
     , Parser
     )
 where
@@ -30,9 +32,13 @@ import           Data.Bits
 import           Data.Functor                (($>))
 import           Data.Functor.Identity       (Identity)
 import           Data.List                   (isInfixOf, isPrefixOf, null)
+import           Data.List.NonEmpty          (NonEmpty (..))
+import           Data.Text                   (Text)
 import qualified Data.Text                   as T
+import qualified Data.Text.IO                as T
 import           Text.Parsec                 hiding (satisfy)
 import           Text.Parsec.Expr
+import           VeriFuzz.Internal
 import           VeriFuzz.Verilog.AST
 import           VeriFuzz.Verilog.BitVec
 import           VeriFuzz.Verilog.Internal
@@ -129,10 +135,14 @@ parseFun = do
     expr <- parens parseExpr
     return $ Appl (Identifier $ T.pack f) expr
 
+parserNonEmpty :: [a] -> Parser (NonEmpty a)
+parserNonEmpty (a:b) = return $ a :| b
+parserNonEmpty []    = fail "Concatenation cannot be empty."
+
 parseTerm :: Parser Expr
 parseTerm =
     parens parseExpr
-        <|> (Concat <$> braces (commaSep parseExpr))
+        <|> (Concat <$> (braces (commaSep parseExpr) >>= parserNonEmpty))
         <|> parseFun
         <|> parseNum
         <|> try parseVecSelect
@@ -476,9 +486,19 @@ parseVerilogSrc = Verilog <$> many parseModDecl
 -- | Parse a 'String' containing verilog code. The parser currently only supports
 -- the subset of Verilog that is being generated randomly.
 parseVerilog
-    :: String -- ^ Name of parsed object.
-    -> String -- ^ Content to be parsed.
-    -> Either String Verilog -- ^ Returns 'String' with error
+    :: Text -- ^ Name of parsed object.
+    -> Text -- ^ Content to be parsed.
+    -> Either Text Verilog -- ^ Returns 'String' with error
                                          -- message if parse fails.
 parseVerilog s =
-    bimap show id . parse parseVerilogSrc s . alexScanTokens . preprocess [] s
+    bimap showT id . parse parseVerilogSrc (T.unpack s) . alexScanTokens . preprocess [] (T.unpack s) . T.unpack
+
+parseVerilogFile :: Text -> IO Verilog
+parseVerilogFile file = do
+    src <- T.readFile $ T.unpack file
+    case parseVerilog file src of
+        Left s  -> error $ T.unpack s
+        Right r -> return r
+
+parseSourceInfoFile :: Text -> Text -> IO SourceInfo
+parseSourceInfoFile top = fmap (SourceInfo top) . parseVerilogFile
diff --git a/src/VeriFuzz/Verilog/Quote.hs b/src/VeriFuzz/Verilog/Quote.hs
index 1450f5e..b252af2 100644
--- a/src/VeriFuzz/Verilog/Quote.hs
+++ b/src/VeriFuzz/Verilog/Quote.hs
@@ -42,8 +42,8 @@ verilog = QuasiQuoter { quoteExp = quoteVerilog
 quoteVerilog :: String -> TH.Q TH.Exp
 quoteVerilog s = do
     loc <- TH.location
-    let pos = TH.loc_filename loc
-    v <- case parseVerilog pos s of
+    let pos = T.pack $ TH.loc_filename loc
+    v <- case parseVerilog pos (T.pack s) of
         Right e -> return e
         Left e  -> fail $ show e
     liftDataWithText v
diff --git a/test/Parser.hs b/test/Parser.hs
index d473e05..40a8f30 100644
--- a/test/Parser.hs
+++ b/test/Parser.hs
@@ -26,6 +26,7 @@ import           Test.Tasty.Hedgehog
 import           Test.Tasty.HUnit
 import           Text.Parsec
 import           VeriFuzz
+import           VeriFuzz.Internal
 import           VeriFuzz.Verilog.Lex
 import           VeriFuzz.Verilog.Parser
 
@@ -69,9 +70,9 @@ parserIdempotent = Hog.property $ do
     let sv = vshow v
     p sv === (p . p) sv
   where
-    vshow = show . GenVerilog
+    vshow = showT . GenVerilog
     p sv =
-        either (\x -> show x <> "\n" <> sv) vshow $ parseVerilog "idempotent_test" sv
+        either (\x -> showT x <> "\n" <> sv) vshow $ parseVerilog "idempotent_test" sv
 
 parserTests :: TestTree
 parserTests = testGroup "Parser properties"