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| author | Yann Herklotz <git@yannherklotz.com> | 2019-07-09 22:02:45 +0200 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-07-09 22:02:45 +0200 |
| commit | 562f0da77e0464bfc21e8753070aec1cf9e60cf2 (patch) | |
| tree | fe2e93cbe91bbe94d08400f931a1c22b4e13d6d8 | |
| parent | 8260ab85db7da1d5de488226991cdac2f302ab25 (diff) | |
| download | verismith-562f0da77e0464bfc21e8753070aec1cf9e60cf2.tar.gz verismith-562f0da77e0464bfc21e8753070aec1cf9e60cf2.zip | |
Fix missing module instantiation
| -rw-r--r-- | src/VeriFuzz/Verilog/Gen.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs index 3bfe4b9..2331068 100644 --- a/src/VeriFuzz/Verilog/Gen.hs +++ b/src/VeriFuzz/Verilog/Gen.hs @@ -362,7 +362,7 @@ instantiate :: ModDecl -> StateGen ModItem instantiate (ModDecl i outP inP _ _) = do context <- get outs <- replicateM (length outP) (nextPort Wire) - ins <- take (length inP - 1) <$> Hog.shuffle (context ^. variables) + ins <- take (length inP) <$> Hog.shuffle (context ^. variables) sequence_ $ uncurry resizePort <$> zip (outs <> ins) (outP <> inP) ident <- makeIdentifier "modinst" Hog.choice |