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author | Yann Herklotz <git@yannherklotz.com> | 2021-07-23 12:52:06 +0200 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2021-07-23 12:52:06 +0200 |
commit | 7cdea045e75f2246243461ae0579c3dfe27f8afb (patch) | |
tree | 1e23ccb8bb32b084d321581b95d4cc7dc1948c5a | |
parent | e8cc0d0d2902ad06133f196ea23c23962ec55b0f (diff) | |
download | verismith-7cdea045e75f2246243461ae0579c3dfe27f8afb.tar.gz verismith-7cdea045e75f2246243461ae0579c3dfe27f8afb.zip |
Fix compilation issues
-rw-r--r-- | src/Verismith.hs | 7 | ||||
-rw-r--r-- | src/Verismith/Shuffle.hs | 6 |
2 files changed, 7 insertions, 6 deletions
diff --git a/src/Verismith.hs b/src/Verismith.hs index 53b2de6..c0c9102 100644 --- a/src/Verismith.hs +++ b/src/Verismith.hs @@ -75,6 +75,7 @@ import Verismith.Verilog import Verismith.Verilog.Distance import Verismith.Verilog.Parser (parseSourceInfoFile) import Verismith.EMI +import Verismith.Shuffle import Prelude hiding (FilePath) toFP :: String -> FilePath @@ -216,9 +217,9 @@ handleOpts (ShuffleOpt f t o nshuffle nrename) = do Left l -> print l Right v -> do let sv = SourceInfo t v - sv' <- if nshuffle then return sv else shuffleLines sv - sv'' <- if nrename then return sv' else renameVariables sv' - case ( o, GenVerilog sv'') of + sv' <- if nshuffle then return sv else shuffleLinesIO sv + sv'' <- if nrename then return sv' else renameVariablesIO sv' + case ( o, GenVerilog sv'' :: GenVerilog (SourceInfo ())) of (Nothing, a) -> print a (Just o', a) -> writeFile (T.unpack $ toTextIgnore o') $ show a where diff --git a/src/Verismith/Shuffle.hs b/src/Verismith/Shuffle.hs index d53b18c..0c460e2 100644 --- a/src/Verismith/Shuffle.hs +++ b/src/Verismith/Shuffle.hs @@ -103,11 +103,11 @@ shuffleLines = applyModules shuffleLinesModule renameVariables = applyModules renameVariablesModule identityMod = applyModules identModule -shuffleLinesIO :: (SourceInfo a) -> Gen (SourceInfo a) +shuffleLinesIO :: (SourceInfo a) -> IO (SourceInfo a) shuffleLinesIO = Hog.sample . shuffleLines -renameVariablesIO :: (SourceInfo a) -> Gen (SourceInfo a) -renameVariablesIO = Hog.sample . renameVariables +renameVariablesIO :: (SourceInfo a) -> IO (SourceInfo a) +renameVariablesIO = Hog.sample . renameVariables m' :: SourceInfo () m' = SourceInfo "m" [verilog| |