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| author | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-30 19:44:00 +0100 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-30 19:44:13 +0100 |
| commit | 9f2bb8aff3198d36ac847dde67e4e630cd8b889f (patch) | |
| tree | fc4233d20ba6e753a879ffb31a810bab6bfcb6ca | |
| parent | dbd13a3bc066b2f07f0856e028a01e28b381bdd9 (diff) | |
| download | verismith-9f2bb8aff3198d36ac847dde67e4e630cd8b889f.tar.gz verismith-9f2bb8aff3198d36ac847dde67e4e630cd8b889f.zip | |
Change modPort type from Maybe to List
| -rw-r--r-- | src/Test/VeriFuzz/Verilog/AST.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/Test/VeriFuzz/Verilog/AST.hs b/src/Test/VeriFuzz/Verilog/AST.hs index 65be816..33ccdb4 100644 --- a/src/Test/VeriFuzz/Verilog/AST.hs +++ b/src/Test/VeriFuzz/Verilog/AST.hs @@ -194,7 +194,7 @@ data ModItem = ModCA ContAssign -- | 'module' module_identifier [list_of_ports] ';' { module_item } 'end_module' data ModDecl = ModDecl { _moduleId :: Identifier - , _modOutPort :: Maybe Port + , _modOutPorts :: [Port] , _modInPorts :: [Port] , _moduleItems :: [ModItem] } deriving (Show, Eq, Ord) |