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| author | Yann Herklotz <git@yannherklotz.com> | 2020-05-13 01:49:01 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2020-05-13 01:49:01 +0100 |
| commit | b8489f292f6a3b08e838b4b2bfb495dea8b74b12 (patch) | |
| tree | 0fa4739bd72f30101a0580644fa1c67dae5154ce | |
| parent | 668eda8ea01553e7788ba4dce888360e54320d9f (diff) | |
| download | verismith-b8489f292f6a3b08e838b4b2bfb495dea8b74b12.tar.gz verismith-b8489f292f6a3b08e838b4b2bfb495dea8b74b12.zip | |
Save out of scope variables
| -rw-r--r-- | src/Verismith/Generate.hs | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/Verismith/Generate.hs b/src/Verismith/Generate.hs index 795d89b..51bd066 100644 --- a/src/Verismith/Generate.hs +++ b/src/Verismith/Generate.hs @@ -92,6 +92,7 @@ data Context a { _wires :: [Port], _nonblocking :: [Port], _blocking :: [Port], + _outofscope :: [Port], _parameters :: [Parameter], _modules :: [ModDecl a], _nameCounter :: {-# UNPACK #-} !Int, @@ -503,6 +504,8 @@ statement = do alwaysSeq :: StateGen ann (ModItem ann) alwaysSeq = do always <- Always . EventCtrl (EPosEdge "clk") . Just <$> seqBlock + blk <- fmap _blocking get + outofscope %= mappend blk blocking .= [] return always @@ -591,10 +594,12 @@ modInst = do let w = _wires context let nb = _nonblocking context let b = _blocking context + let oos = _outofscope context modules .= [] wires .= [] nonblocking .= [] blocking .= [] + outofscope .= [] parameters .= [] modDepth -= 1 chosenMod <- moduleDef Nothing @@ -605,6 +610,7 @@ modInst = do wires .= w nonblocking .= nb blocking .= b + outofscope .= oos modules .= chosenMod : currMods <> genMods instantiate chosenMod else Hog.element (context ^. modules) >>= instantiate @@ -707,7 +713,7 @@ moduleDef top = do context <- get vars <- shareableVariables config <- ask - let (newPorts, local) = partition (`identElem` portList) $ vars + let (newPorts, local) = partition (`identElem` portList) $ vars <> _outofscope context let size = evalRange (_parameters context) 32 . sum @@ -738,7 +744,7 @@ procedural top config = do return . Verilog $ mainMod : st ^. modules where context = - Context [] [] [] [] [] 0 (confProp propStmntDepth) (confProp propModDepth) True + Context [] [] [] [] [] [] 0 (confProp propStmntDepth) (confProp propModDepth) True num = fromIntegral $ confProp propSize confProp i = config ^. configProperty . i |