Rename some functions to use nicer names

10 files changed, 62 insertions, 55 deletions

diff --git a/src/VeriFuzz.hs b/src/VeriFuzz.hs
index 84d3336..cbbfb9a 100644
--- a/src/VeriFuzz.hs
+++ b/src/VeriFuzz.hs
@@ -121,11 +121,11 @@ onFailure t _ = do
     ex <- lastExitCode
     case ex of
         124 -> do
-            echoP "Test TIMEOUT"
+            logger "Test TIMEOUT"
             chdir ".." $ cp_r (fromText t) $ fromText (t <> "_timeout")
             return $ Fail EmptyFail
         _ -> do
-            echoP "Test FAIL"
+            logger "Test FAIL"
             chdir ".." $ cp_r (fromText t) $ fromText (t <> "_failed")
             return $ Fail EmptyFail
 
@@ -169,14 +169,14 @@ runEquivalence seed gm t d k i = do
                                 defaultYosys
                                 (Just defaultVivado)
                                 srcInfo
-                    >> liftSh (echoP "Test OK")
+                    >> liftSh (logger "Test OK")
                     )
                 $ onFailure n
         _ <-
             catch_sh
                     (   runResultT
                     $   runSim (Icarus "iverilog" "vvp") srcInfo rand
-                    >>= (\b -> liftSh $ echoP ("RTL Sim: " <> showBS b))
+                    >>= (\b -> liftSh $ logger ("RTL Sim: " <> showBS b))
                     )
                 $ onFailure n
         cd ".."
diff --git a/src/VeriFuzz/Config.hs b/src/VeriFuzz/Config.hs
index 1a2681a..523c743 100644
--- a/src/VeriFuzz/Config.hs
+++ b/src/VeriFuzz/Config.hs
@@ -270,28 +270,28 @@ defaultConfig = Config
   where
     defModItem =
         ProbModItem 5 -- Assign
-                    1 -- Always
-                    1 -- Instantiation
+                      1 -- Always
+                        1 -- Instantiation
     defStmnt =
         ProbStatement 0 -- Blocking assignment
-                      3 -- Non-blocking assignment
-                      1 -- Conditional
-                      0 -- For loop
+                        3 -- Non-blocking assignment
+                          1 -- Conditional
+                            0 -- For loop
     defExpr =
         ProbExpr 1 -- Number
-                 5 -- Identifier
-                 5 -- Range selection
-                 5 -- Unary operator
-                 5 -- Binary operator
-                 5 -- Ternary conditional
-                 3 -- Concatenation
-                 0 -- String
-                 5 -- Signed function
-                 5 -- Unsigned funtion
+                   5 -- Identifier
+                     5 -- Range selection
+                       5 -- Unary operator
+                         5 -- Binary operator
+                           5 -- Ternary conditional
+                             3 -- Concatenation
+                               0 -- String
+                                 5 -- Signed function
+                                   5 -- Unsigned funtion
     defEvent =
         ProbEventList 0 -- All
-                      1 -- Clk
-                      0 -- Var
+                        1 -- Clk
+                          0 -- Var
 
 twoKey :: Toml.Piece -> Toml.Piece -> Toml.Key
 twoKey a b = Toml.Key (a :| [b])
diff --git a/src/VeriFuzz/Fuzz.hs b/src/VeriFuzz/Fuzz.hs
index 553fc88..5f0ccfb 100644
--- a/src/VeriFuzz/Fuzz.hs
+++ b/src/VeriFuzz/Fuzz.hs
@@ -88,7 +88,7 @@ combinations :: [a] -> [b] -> [(a, b)]
 combinations l1 l2 = [ (x, y) | x <- l1, y <- l2 ]
 
 logT :: MonadSh m => Text -> m ()
-logT = liftSh . echoP
+logT = liftSh . logger
 
 timeit :: (MonadIO m, MonadSh m) => m a -> m (NominalDiffTime, a)
 timeit a = do
diff --git a/src/VeriFuzz/Sim.hs b/src/VeriFuzz/Sim.hs
index 0736856..9b96894 100644
--- a/src/VeriFuzz/Sim.hs
+++ b/src/VeriFuzz/Sim.hs
@@ -34,7 +34,7 @@ module VeriFuzz.Sim
     , runSim
     -- * Synthesis
     , runSynth
-    , echoP
+    , logger
     )
 where
 
diff --git a/src/VeriFuzz/Sim/Icarus.hs b/src/VeriFuzz/Sim/Icarus.hs
index ec79340..062a087 100644
--- a/src/VeriFuzz/Sim/Icarus.hs
+++ b/src/VeriFuzz/Sim/Icarus.hs
@@ -113,10 +113,11 @@ runSimIcarusWithFile
     :: Icarus -> FilePath -> [ByteString] -> ResultSh ByteString
 runSimIcarusWithFile sim f _ = annotate SimFail . liftSh $ do
     dir <- pwd
-    echoP "Icarus: Compile"
-    logger_ dir "icarus" $ run (icarusPath sim) ["-o", "main", toTextIgnore f]
-    echoP "Icarus: Run"
-    B.take 8 . BA.convert . (hash :: ByteString -> Digest SHA256) <$> logger
+    logger "Icarus: Compile"
+    logCommand_ dir "icarus"
+        $ run (icarusPath sim) ["-o", "main", toTextIgnore f]
+    logger "Icarus: Run"
+    B.take 8 . BA.convert . (hash :: ByteString -> Digest SHA256) <$> logCommand
         dir
         "vvp"
         (runFoldLines (mempty :: ByteString) callback (vvpPath sim) ["main"])
diff --git a/src/VeriFuzz/Sim/Internal.hs b/src/VeriFuzz/Sim/Internal.hs
index 6d36348..06d0264 100644
--- a/src/VeriFuzz/Sim/Internal.hs
+++ b/src/VeriFuzz/Sim/Internal.hs
@@ -27,9 +27,9 @@ module VeriFuzz.Sim.Internal
     , timeout_
     , bsToI
     , noPrint
-    , echoP
     , logger
-    , logger_
+    , logCommand
+    , logCommand_
     , execute
     , execute_
     , (<?>)
@@ -105,13 +105,16 @@ checkPresent fp t = do
 -- may have been inlined. This could be improved if the parser worked properly.
 checkPresentModules :: FilePath -> SourceInfo -> Sh [Text]
 checkPresentModules fp (SourceInfo _ src) = do
-    vals <- forM (src ^.. _Wrapped . traverse . modId . _Wrapped) $ checkPresent fp
+    vals <- forM (src ^.. _Wrapped . traverse . modId . _Wrapped)
+        $ checkPresent fp
     return $ catMaybes vals
 
 -- | Uses sed to replace a string in a text file.
 replace :: FilePath -> Text -> Text -> Sh ()
 replace fp t1 t2 = do
-    errExit False . noPrint $ run_ "sed" ["-i", "s/" <> t1 <> "/" <> t2 <> "/g", toTextIgnore fp]
+    errExit False . noPrint $ run_
+        "sed"
+        ["-i", "s/" <> t1 <> "/" <> t2 <> "/g", toTextIgnore fp]
 
 -- | This is used because rename only renames the definitions of modules of
 -- course, so instead this just searches and replaces all the module names. This
@@ -119,7 +122,9 @@ replace fp t1 t2 = do
 -- much simpler if the parser works.
 replaceMods :: FilePath -> Text -> SourceInfo -> Sh ()
 replaceMods fp t (SourceInfo _ src) =
-    void . forM (src ^.. _Wrapped . traverse . modId . _Wrapped) $ (\a -> replace fp a (a <> t))
+    void
+        . forM (src ^.. _Wrapped . traverse . modId . _Wrapped)
+        $ (\a -> replace fp a (a <> t))
 
 rootPath :: Sh FilePath
 rootPath = do
@@ -143,21 +148,22 @@ noPrint :: Sh a -> Sh a
 noPrint = print_stdout False . print_stderr False
 {-# INLINE noPrint #-}
 
-echoP :: Text -> Sh ()
-echoP t = do
+logger :: Text -> Sh ()
+logger t = do
     fn          <- pwd
     currentTime <- liftIO getZonedTime
     echo $ bname fn <> " [" <> showT currentTime <> "] - " <> t
     where bname = T.pack . takeBaseName . T.unpack . toTextIgnore
 
-logger :: FilePath -> Text -> Sh a -> Sh a
-logger fp name = log_stderr_with (l "_stderr.log") . log_stdout_with (l ".log")
+logCommand :: FilePath -> Text -> Sh a -> Sh a
+logCommand fp name = log_stderr_with (l "_stderr.log")
+    . log_stdout_with (l ".log")
   where
     l s t = appendFile (file s) (T.unpack t) >> appendFile (file s) "\n"
     file s = T.unpack (toTextIgnore $ fp </> fromText name) <> s
 
-logger_ :: FilePath -> Text -> Sh a -> Sh ()
-logger_ fp name = void . logger fp name
+logCommand_ :: FilePath -> Text -> Sh a -> Sh ()
+logCommand_ fp name = void . logCommand fp name
 
 execute
     :: (MonadSh m, Monad m, Monoid a)
@@ -167,7 +173,7 @@ execute
     -> FilePath
     -> [Text]
     -> ResultT a m Text
-execute f dir name e = annotate f . liftSh . logger dir name . timeout e
+execute f dir name e = annotate f . liftSh . logCommand dir name . timeout e
 
 execute_
     :: (MonadSh m, Monad m, Monoid a)
diff --git a/src/VeriFuzz/Sim/Quartus.hs b/src/VeriFuzz/Sim/Quartus.hs
index 0559637..5f3c18c 100644
--- a/src/VeriFuzz/Sim/Quartus.hs
+++ b/src/VeriFuzz/Sim/Quartus.hs
@@ -48,7 +48,7 @@ runSynthQuartus sim (SourceInfo top src) = do
     let ex = execute_ SynthFail dir "quartus"
     liftSh $ do
         writefile inpf $ genSource src
-        echoP "Running Quartus synthesis"
+        logger "Running Quartus synthesis"
     ex (exec "quartus_map")
        [top, "--source=" <> toTextIgnore inpf, "--family=Cyclone V"]
     ex (exec "quartus_fit") [top, "--part=5CGXFC7D6F31C6"]
@@ -62,7 +62,7 @@ runSynthQuartus sim (SourceInfo top src) = do
             , "s,^// DATE.*,,; s,^tri1 (.*);,wire \\1 = 1;,; /^\\/\\/ +synopsys/ d;"
             , toTextIgnore $ synthOutput sim
             ]
-        echoP "Quartus synthesis done"
+        logger "Quartus synthesis done"
   where
     inpf = "rtl.v"
     exec s = maybe (fromText s) (</> fromText s) $ quartusBin sim
diff --git a/src/VeriFuzz/Sim/Vivado.hs b/src/VeriFuzz/Sim/Vivado.hs
index 1994a57..bff4d7c 100644
--- a/src/VeriFuzz/Sim/Vivado.hs
+++ b/src/VeriFuzz/Sim/Vivado.hs
@@ -51,11 +51,11 @@ runSynthVivado sim (SourceInfo top src) = do
             sim
         writefile "rtl.v" $ genSource src
         run_ "sed" ["s/^module/(* use_dsp=\"no\" *) module/;", "-i", "rtl.v"]
-        echoP "Vivado: run"
+        logger "Vivado: run"
     execute_ SynthFail
              dir
              "vivado"
              (vivadoPath sim)
              ["-mode", "batch", "-source", toTextIgnore vivadoTcl]
-    liftSh $ echoP "Vivado: done"
+    liftSh $ logger "Vivado: done"
     where vivadoTcl = fromText ("vivado_" <> top) <.> "tcl"
diff --git a/src/VeriFuzz/Sim/XST.hs b/src/VeriFuzz/Sim/XST.hs
index 324f227..92dcaa1 100644
--- a/src/VeriFuzz/Sim/XST.hs
+++ b/src/VeriFuzz/Sim/XST.hs
@@ -55,9 +55,9 @@ runSynthXST sim (SourceInfo top src) = do
         writefile xstFile $ xstSynthConfig top
         writefile prjFile [st|verilog work "rtl.v"|]
         writefile "rtl.v" $ genSource src
-        echoP "XST: run"
+        logger "XST: run"
     exec (xstPath sim) ["-ifn", toTextIgnore xstFile]
-    liftSh $ echoP "XST: netgen"
+    liftSh $ logger "XST: netgen"
     exec
         (netgenPath sim)
         [ "-w"
@@ -67,14 +67,14 @@ runSynthXST sim (SourceInfo top src) = do
         , toTextIgnore $ synthOutput sim
         ]
     liftSh $ do
-        echoP "XST: clean"
+        logger "XST: clean"
         noPrint $ run_
             "sed"
             [ "-i"
             , "/^`ifndef/,/^`endif/ d; s/ *Timestamp: .*//;"
             , toTextIgnore $ synthOutput sim
             ]
-        echoP "XST: done"
+        logger "XST: done"
   where
     modFile = fromText top
     xstFile = modFile <.> "xst"
diff --git a/src/VeriFuzz/Sim/Yosys.hs b/src/VeriFuzz/Sim/Yosys.hs
index 1bff975..80fb5b5 100644
--- a/src/VeriFuzz/Sim/Yosys.hs
+++ b/src/VeriFuzz/Sim/Yosys.hs
@@ -54,12 +54,12 @@ runSynthYosys :: Yosys -> SourceInfo -> ResultSh ()
 runSynthYosys sim (SourceInfo _ src) = (<?> SynthFail) . liftSh $ do
     dir <- pwd
     writefile inpf $ genSource src
-    echoP "Yosys: synthesis"
-    logger_ dir "yosys"
+    logger "Yosys: synthesis"
+    logCommand_ dir "yosys"
         $ timeout
               (yosysPath sim)
               ["-b", "verilog -noattr", "-o", out, "-S", inp]
-    echoP "Yosys: synthesis done"
+    logger "Yosys: synthesis done"
   where
     inpf = "rtl.v"
     inp  = toTextIgnore inpf
@@ -89,9 +89,9 @@ runEquivYosys yosys sim1 sim2 srcInfo = do
     runSynth sim1 srcInfo
     runMaybeSynth sim2 srcInfo
     liftSh $ do
-        echoP "Yosys: equivalence check"
+        logger "Yosys: equivalence check"
         run_ (yosysPath yosys) [toTextIgnore checkFile]
-        echoP "Yosys: equivalence done"
+        logger "Yosys: equivalence done"
   where
     checkFile =
         fromText [st|test.#{toText sim1}.#{maybe "rtl" toText sim2}.ys|]
@@ -104,7 +104,7 @@ runEquiv
     -> SourceInfo
     -> ResultSh ()
 runEquiv _ sim1 sim2 srcInfo = do
-    dir  <- liftSh pwd
+    dir <- liftSh pwd
     liftSh $ do
         writefile "top.v"
             .  genSource
@@ -112,9 +112,9 @@ runEquiv _ sim1 sim2 srcInfo = do
             .  makeTopAssert
             $  srcInfo
             ^. mainModule
-        replaceMods (synthOutput sim1) "_1" srcInfo
+        replaceMods (synthOutput sim1)               "_1" srcInfo
         replaceMods (maybe "rtl.v" synthOutput sim2) "_2" srcInfo
         writefile "test.sby" $ sbyConfig sim1 sim2 srcInfo
-    liftSh $ echoP "Running SymbiYosys"
+    liftSh $ logger "Running SymbiYosys"
     execute_ EquivFail dir "symbiyosys" "sby" ["-f", "test.sby"]
-    liftSh $ echoP "SymbiYosys equivalence check passed"
+    liftSh $ logger "SymbiYosys equivalence check passed"