Change Port type to include lower bound

6 files changed, 24 insertions, 25 deletions

diff --git a/src/VeriFuzz/Circuit/Gen.hs b/src/VeriFuzz/Circuit/Gen.hs
index 0b13ece..1e31e56 100644
--- a/src/VeriFuzz/Circuit/Gen.hs
+++ b/src/VeriFuzz/Circuit/Gen.hs
@@ -38,7 +38,7 @@ inputsC :: Circuit -> [Node]
 inputsC c = inputs (getCircuit c)
 
 genPortsAST :: (Circuit -> [Node]) -> Circuit -> [Port]
-genPortsAST f c = port . frNode <$> f c where port = Port Wire False 4
+genPortsAST f c = port . frNode <$> f c where port = Port Wire False 0 4
 
 -- | Generates the nested expression AST, so that it can then generate the
 -- assignment expressions.
@@ -73,7 +73,7 @@ genModuleDeclAST c = ModDecl i output ports (combineAssigns yPort a) []
     ports  = genPortsAST inputsC c
     output = []
     a      = genAssignAST c
-    yPort  = Port Wire False 90 "y"
+    yPort  = Port Wire False 0 90 "y"
 
 generateAST :: Circuit -> Verilog
 generateAST c = Verilog [genModuleDeclAST c]
diff --git a/src/VeriFuzz/Sim/Reduce.hs b/src/VeriFuzz/Sim/Reduce.hs
index 381a84c..361df3e 100644
--- a/src/VeriFuzz/Sim/Reduce.hs
+++ b/src/VeriFuzz/Sim/Reduce.hs
@@ -67,8 +67,8 @@ filterExpr ids (Id i) = if i `notElem` ids then Number 1 0 else Id i
 filterExpr _   e      = e
 
 filterDecl :: [Identifier] -> ModItem -> Bool
-filterDecl ids (Decl Nothing (Port _ _ _ i) _) = i `elem` ids
-filterDecl _   _                               = True
+filterDecl ids (Decl Nothing (Port _ _ _ _ i) _) = i `elem` ids
+filterDecl _   _                                 = True
 
 filterAssigns :: [Port] -> ModItem -> Bool
 filterAssigns out (ModCA (ContAssign i _)) =
diff --git a/src/VeriFuzz/Verilog.hs b/src/VeriFuzz/Verilog.hs
index 19dc607..4d3b82c 100644
--- a/src/VeriFuzz/Verilog.hs
+++ b/src/VeriFuzz/Verilog.hs
@@ -114,14 +114,9 @@ module VeriFuzz.Verilog
     -- * Useful Lenses and Traversals
     , getModule
     , getSourceId
-    -- * Arbitrary
-    , Arb
-    , arb
-    , genPositive
     )
 where
 
-import           VeriFuzz.Verilog.Arbitrary
 import           VeriFuzz.Verilog.AST
 import           VeriFuzz.Verilog.CodeGen
 import           VeriFuzz.Verilog.Gen
diff --git a/src/VeriFuzz/Verilog/Internal.hs b/src/VeriFuzz/Verilog/Internal.hs
index d68e46c..63072b1 100644
--- a/src/VeriFuzz/Verilog/Internal.hs
+++ b/src/VeriFuzz/Verilog/Internal.hs
@@ -33,10 +33,10 @@ import           Data.Text            (Text)
 import           VeriFuzz.Verilog.AST
 
 regDecl :: Identifier -> ModItem
-regDecl i = Decl Nothing (Port Reg False 1 i) Nothing
+regDecl i = Decl Nothing (Port Reg False 0 1 i) Nothing
 
 wireDecl :: Identifier -> ModItem
-wireDecl i = Decl Nothing (Port Wire False 1 i) Nothing
+wireDecl i = Decl Nothing (Port Wire False 0 1 i) Nothing
 
 -- | Create an empty module.
 emptyMod :: ModDecl
@@ -82,19 +82,19 @@ addTestBench :: Verilog -> Verilog
 addTestBench = addModDecl testBench
 
 defaultPort :: Identifier -> Port
-defaultPort = Port Wire False 1
+defaultPort = Port Wire False 0 1
 
 portToExpr :: Port -> Expr
-portToExpr (Port _ _ _ i) = Id i
+portToExpr (Port _ _ _ _ i) = Id i
 
 modName :: ModDecl -> Text
 modName = view $ modId . getIdentifier
 
 yPort :: Identifier -> Port
-yPort = Port Wire False 90
+yPort = Port Wire False 0 90
 
 wire :: Int -> Identifier -> Port
-wire = Port Wire False
+wire = Port Wire False 0
 
 reg :: Int -> Identifier -> Port
-reg = Port Reg False
+reg = Port Reg False 0
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs
index e170680..f4330bc 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Verilog/Mutate.hs
@@ -124,11 +124,14 @@ allVars m =
 instantiateMod :: ModDecl -> ModDecl -> ModDecl
 instantiateMod m main = main & modItems %~ ((out ++ regIn ++ [inst]) ++)
   where
-    out   = Decl Nothing <$> m ^. modOutPorts <*> pure Nothing
-    regIn = Decl Nothing <$> (m ^. modInPorts & traverse . portType .~ Reg) <*> pure Nothing
-    inst  = ModInst (m ^. modId)
-                    (m ^. modId <> (Identifier . showT $ count + 1))
-                    conns
+    out = Decl Nothing <$> m ^. modOutPorts <*> pure Nothing
+    regIn =
+        Decl Nothing
+            <$> (m ^. modInPorts & traverse . portType .~ Reg)
+            <*> pure Nothing
+    inst = ModInst (m ^. modId)
+                   (m ^. modId <> (Identifier . showT $ count + 1))
+                   conns
     count =
         length
             .   filter (== m ^. modId)
@@ -216,9 +219,10 @@ makeTopAssert = (modItems %~ (++ [assert])) . makeTop 2
 -- registers, it should assign them to 0.
 declareMod :: [Port] -> ModDecl -> ModDecl
 declareMod ports = initMod . (modItems %~ (decl ++))
-    where decl = declf <$> ports
-          declf p@(Port Reg _ _ _) = Decl Nothing p (Just 0)
-          declf p                  = Decl Nothing p Nothing
+  where
+    decl = declf <$> ports
+    declf p@(Port Reg _ _ _ _) = Decl Nothing p (Just 0)
+    declf p                    = Decl Nothing p Nothing
 
 -- | Simplify an 'Expr' by using constants to remove 'BinaryOperator' and
 -- simplify expressions. To make this work effectively, it should be run until
diff --git a/src/VeriFuzz/Verilog/Parser.hs b/src/VeriFuzz/Verilog/Parser.hs
index 3b07366..518bcb9 100644
--- a/src/VeriFuzz/Verilog/Parser.hs
+++ b/src/VeriFuzz/Verilog/Parser.hs
@@ -259,7 +259,7 @@ parseNetDecl pd = do
     range <- option 1 parseRange
     name  <- identifier
     tok' SymSemi
-    return $ Decl pd (Port t sign range name) Nothing
+    return $ Decl pd (Port t sign 0 range name) Nothing
     where type_ = tok KWWire $> Wire <|> tok KWReg $> Reg
 
 parsePortDir :: Parser PortDir