Update adding info for commercial license

2 files changed, 9 insertions, 1 deletions

diff --git a/LICENSE b/LICENSE
index be47c3b..d8331bd 100644
--- a/LICENSE
+++ b/LICENSE
@@ -1,6 +1,10 @@
 Verismith can be used under two licenses, either the GPLv3 license or a
 commercial license from Imperial College London.
 
+For commercial use you need a Software Usage Agreement from Imperial
+College London. Otherwise the software is released under the GPLv3
+license shown below.
+
 ------------------------------------------------------------------------
 
                     GNU GENERAL PUBLIC LICENSE
diff --git a/README.md b/README.md
index bc270d0..398a7d6 100644
--- a/README.md
+++ b/README.md
@@ -29,7 +29,7 @@ The fuzzer generates combinational and behavioural Verilog to test the various t
 
 ## Reported bugs
 
-9 bugs have been reported and confirmed to be bugs by the vendors, out of which 4 have been fixed. 1 bug has also been found in the Icarus Verilog simulator as a side effect of using it to verify equivalence check results.
+11 bugs have been reported and confirmed to be bugs by the vendors, out of which 4 have been fixed. 1 bug has also been found in the Icarus Verilog simulator as a side effect of using it to verify equivalence check results.
 
 ### Yosys
 
@@ -204,6 +204,10 @@ If you use Verismith in your research, please cite our [FPGA '20 paper](https://
 }
 ```
 
+## License
+
+Verismith is not free software. This non-commercial release can only be used for evaluation, research, educational and personal purposes. A commercial version of Verismith, without this restriction and with professional support, can be purchased from Imperial College London. See the file [LICENSE](/LICENSE) for more information.
+
 ## Acknowledgement
 
 Clifford Wolf's [VlogHammer](http://www.clifford.at/yosys/vloghammer.html) is an existing Verilog fuzzer that generates random Verilog to test how expressions are handled in synthesis tools and simulators. It was the inspiration for thegeneral structure of this fuzzer, which extends the fuzzing to the behavioural parts of Verilog.