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author | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-29 19:40:24 +0100 |
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committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-29 19:40:24 +0100 |
commit | 83ad6d594a76d9b9b55e8027df94ad7ae22b0ff3 (patch) | |
tree | 3e95a9951c045364d3201461de91b90539d316fd /README.md | |
parent | 6b44a10c288d5d228bd6465df9af2d4ad15219a1 (diff) | |
download | verismith-83ad6d594a76d9b9b55e8027df94ad7ae22b0ff3.tar.gz verismith-83ad6d594a76d9b9b55e8027df94ad7ae22b0ff3.zip |
Add more info to README
Diffstat (limited to 'README.md')
-rw-r--r-- | README.md | 11 |
1 files changed, 8 insertions, 3 deletions
@@ -1,5 +1,10 @@ -![Build Status](https://travis-ci.com/ymherklotz/verifuzz.svg?token=qfBKKGwxeWkjDsy7e16x&branch=master) +# VeriFuzz ![Build Status](https://travis-ci.com/ymherklotz/verifuzz.svg?token=qfBKKGwxeWkjDsy7e16x&branch=master) -# verifuzz +Verilog Fuzzer to test the major verilog compilers by generating random, valid +verilog. -Verilog Fuzzer to test the major verilog compilers by generating random, valid verilog. +It currently supports the following simulators: + +- [Yosys](http://www.clifford.at/yosys/) +- [Icarus Verilog](http://iverilog.icarus.com) +- [Xst](https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_using_xst_for_synthesis.htm) |