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| author | Yann Herklotz <git@yannherklotz.com> | 2019-07-05 13:52:46 +0200 |
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| committer | Yann Herklotz <git@yannherklotz.com> | 2019-07-05 13:52:46 +0200 |
| commit | e41bb1cddbaf20f96a03e86ba5f0afb47983301d (patch) | |
| tree | dd8b47c6b63722650b6e161199a4d6e9d449fc69 /README.md | |
| parent | 4d2dda8996e19f35a9dd3aa093e78ba48b62c91b (diff) | |
| download | verismith-e41bb1cddbaf20f96a03e86ba5f0afb47983301d.tar.gz verismith-e41bb1cddbaf20f96a03e86ba5f0afb47983301d.zip | |
Small changes to the documentation
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 31 |
1 files changed, 14 insertions, 17 deletions
@@ -1,12 +1,12 @@ # VeriFuzz [](https://travis-ci.com/ymherklotz/verifuzz) Verilog Fuzzer to test the major verilog compilers by generating random, valid -verilog. There is a +and deterministic Verilog. There is a [presentation](https://yannherklotz.com/docs/presentation.pdf) about VeriFuzz and a [thesis](https://yannherklotz.com/docs/thesis.pdf) which goes over all the details of the implementation and results that were found. -It currently supports the following synthesisers: +It currently supports the following synthesis tools: - [Yosys](http://www.clifford.at/yosys/) - [Xst](https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_using_xst_for_synthesis.htm) @@ -38,26 +38,23 @@ following: 21 bugs were found in total over the course of a month. 8 of those bugs were reported and 3 were fixed. -- **MS** :: Mis-synthesis -- **C** :: Crash - ### Yosys -| Type | Issue | Confirmed | Fixed | -|------|------------------------------------------------------------|-----------|-------| -| MS | [Issue 1047](https://github.com/YosysHQ/yosys/issues/1047) | ✓ | ✓ | -| MS | [Issue 997](https://github.com/YosysHQ/yosys/issues/997) | ✓ | ✓ | -| C | [Issue 993](https://github.com/YosysHQ/yosys/issues/993) | ✓ | ✓ | +| Type | Issue | Confirmed | Fixed | +|---------------|------------------------------------------------------------|-----------|-------| +| Mis-synthesis | [Issue 1047](https://github.com/YosysHQ/yosys/issues/1047) | ✓ | ✓ | +| Mis-synthesis | [Issue 997](https://github.com/YosysHQ/yosys/issues/997) | ✓ | ✓ | +| Crash | [Issue 993](https://github.com/YosysHQ/yosys/issues/993) | ✓ | ✓ | ### Vivado -| Type | Issue | Confirmed | Fixed | -|------|-------------------------------------------------------------------------------------------------------------------------------------|-----------|-------| -| C | [Forum 981787](https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Verilog-If-statement-nesting-crash/td-p/981787) | ✓ | 𐄂 | -| C | [Forum 981136](https://forums.xilinx.com/t5/Synthesis/Vivado-2018-3-synthesis-crash/td-p/981136) | ✓ | 𐄂 | -| MS | [Forum 981789](https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Unsigned-bit-extension-in-if-statement/td-p/981789) | ✓ | 𐄂 | -| MS | [Forum 982518](https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Signed-with-shift-in-condition-synthesis-mistmatch/td-p/982518) | ✓ | 𐄂 | -| MS | [Forum 982419](https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Bit-selection-synthesis-mismatch/td-p/982419) | ✓ | 𐄂 | +| Type | Issue | Confirmed | Fixed | +|---------------|-------------------------------------------------------------------------------------------------------------------------------------|-----------|-------| +| Crash | [Forum 981787](https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Verilog-If-statement-nesting-crash/td-p/981787) | ✓ | 𐄂 | +| Crash | [Forum 981136](https://forums.xilinx.com/t5/Synthesis/Vivado-2018-3-synthesis-crash/td-p/981136) | ✓ | 𐄂 | +| Mis-synthesis | [Forum 981789](https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Unsigned-bit-extension-in-if-statement/td-p/981789) | ✓ | 𐄂 | +| Mis-synthesis | [Forum 982518](https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Signed-with-shift-in-condition-synthesis-mistmatch/td-p/982518) | ✓ | 𐄂 | +| Mis-synthesis | [Forum 982419](https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Bit-selection-synthesis-mismatch/td-p/982419) | ✓ | 𐄂 | ## Build the Fuzzer |