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| author | Yann Herklotz <git@yannherklotz.com> | 2019-11-14 16:49:42 +0000 |
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| committer | Yann Herklotz <git@yannherklotz.com> | 2019-11-14 16:49:42 +0000 |
| commit | e827635e34079c8ee9c9e7273a59c905274e553d (patch) | |
| tree | 5ea082d8120a740af3aeea13eb4565f2ade55c7c /README.md | |
| parent | 798f54c05376ec3b4ebbe8326d0a91eec807df3d (diff) | |
| download | verismith-e827635e34079c8ee9c9e7273a59c905274e553d.tar.gz verismith-e827635e34079c8ee9c9e7273a59c905274e553d.zip | |
Update bug reports
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -29,7 +29,7 @@ The fuzzer generates combinational and behavioural Verilog to test the various t ## Reported bugs -9 bugs have been reported and confirmed to be bugs by the vendors, out of which 4 have been fixed. +9 bugs have been reported and confirmed to be bugs by the vendors, out of which 4 have been fixed. 1 bug has also been found in the Icarus Verilog simulator as a side effect of using it to verify equivalence check results. ### Yosys |