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| author | Yann Herklotz <ymherklotz@gmail.com> | 2019-02-07 18:13:12 +0000 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-02-07 18:13:12 +0000 |
| commit | 2d5a02e645e580c5f90f98dc70388f4586a0fb42 (patch) | |
| tree | c58c03dbaa0c0e1005bfc835a35993081d040fe7 /app | |
| parent | d9765414ef70ef22f33d1f75fe0f4ba33b08a69d (diff) | |
| download | verismith-2d5a02e645e580c5f90f98dc70388f4586a0fb42.tar.gz verismith-2d5a02e645e580c5f90f98dc70388f4586a0fb42.zip | |
Fix bracket error
Diffstat (limited to 'app')
| -rw-r--r-- | app/Simulation.hs | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/app/Simulation.hs b/app/Simulation.hs index 91dec33..c5ae952 100644 --- a/app/Simulation.hs +++ b/app/Simulation.hs @@ -88,12 +88,12 @@ runEquivalence gm t i = do catch_sh (runSim (Icarus "iverilog" "vvp") m rand >>= (\b -> echoP ("RTL Sim: " <> showBS b))) $ onFailure n - catch_sh (runSimWithFile (Icarus "iverilog" "vvp") "syn_yosys.v" rand - --AZZZZZZZZZQaa-- >>= (\b -> echoP ("Yosys Sim1q``````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````q-a----------aaaaaaaaaa: " <> showBS b))) $ - onFailure n - catch_sh (runSimWithFile (Icarus "iverilog" "vvp") "syn_xst.v" rand - >>= (\b -> echoP ("XST Sim: " <> showBS b))) $ - onFailure n +-- catch_sh (runSimWithFile (Icarus "iverilog" "vvp") "syn_yosys.v" rand +-- >>= (\b -> echoP ("Yosys Sim: " <> showBS b))) $ +-- onFailure n +-- catch_sh (runSimWithFile (Icarus "iverilog" "vvp") "syn_xst.v" rand +-- >>= (\b -> echoP ("XST Sim: " <> showBS b))) $ +-- onFailure n cd ".." rm_rf $ fromText n when (i < 5) (runEquivalence gm t $ i+1) |