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| author | Yann Herklotz <git@ymhg.org> | 2019-04-01 10:55:40 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-01 10:55:40 +0100 |
| commit | bac2f24871d95eeb3aa3fc898a7656fc4f5f094a (patch) | |
| tree | abae8302d3a07eec39fe1a3d05077d4505a0b2bb /app | |
| parent | ce3b5a9dc47c2325e1e9cc61279972048b9fbabd (diff) | |
| download | verismith-bac2f24871d95eeb3aa3fc898a7656fc4f5f094a.tar.gz verismith-bac2f24871d95eeb3aa3fc898a7656fc4f5f094a.zip | |
Run through brittany
Diffstat (limited to 'app')
| -rw-r--r-- | app/Main.hs | 51 |
1 files changed, 27 insertions, 24 deletions
diff --git a/app/Main.hs b/app/Main.hs index f9ecb52..c214929 100644 --- a/app/Main.hs +++ b/app/Main.hs @@ -66,30 +66,33 @@ fuzzOpts = Fuzz <$> textOption rerunOpts :: Parser Opts rerunOpts = Rerun - <$> some (option - (optReader parseSynth) - ( long "synth" - <> metavar "SYNTH" - <> help "Rerun using a synthesiser (yosys|xst)." - <> showDefault - <> value Yosys - ) - <|> option - (optReader parseSim) - ( long "sim" - <> metavar "SIM" - <> help "Rerun using a simulator (icarus)." - <> showDefault - <> value Icarus - ) - ) + <$> some + ( option + (optReader parseSynth) + ( long "synth" + <> metavar "SYNTH" + <> help "Rerun using a synthesiser (yosys|xst)." + <> showDefault + <> value Yosys + ) + <|> option + (optReader parseSim) + ( long "sim" + <> metavar "SIM" + <> help "Rerun using a simulator (icarus)." + <> showDefault + <> value Icarus + ) + ) <*> (S.fromText <$> textOption - ( long "input" - <> short 'i' - <> metavar "FILE" - <> help "Verilog file input." - <> showDefault - <> value "rtl.v")) + ( long "input" + <> short 'i' + <> metavar "FILE" + <> help "Verilog file input." + <> showDefault + <> value "rtl.v" + ) + ) genOpts :: Parser Opts genOpts = Generate . S.fromText <$> textOption @@ -205,7 +208,7 @@ handleOpts (Parse f) = do Left l -> print l Right v -> print $ V.GenVerilog v where file = T.unpack . S.toTextIgnore $ f -handleOpts (Rerun _ _) = undefined +handleOpts (Rerun _ _) = undefined handleOpts (Reduce f t) = do verilogSrc <- readFile file case V.parseVerilog file verilogSrc of |