Update bug

1 files changed, 10 insertions, 0 deletions

diff --git a/bugs/quartus_12.md b/bugs/quartus_12.md
index 9d8b278..24469ce 100644
--- a/bugs/quartus_12.md
+++ b/bugs/quartus_12.md
@@ -17,3 +17,13 @@ module top(y, wire1);
   assign y = 2'b11 ^ $signed(wire1);
 endmodule
 ```
+
+When Quartus is passed the following design instead, it does output the right result which is `2'b10`.
+
+```verilog
+module top(y, wire1);
+  output [1:0] y;
+  input signed wire1;
+  assign y = 2'b11 ^ wire1;
+endmodule
+```