Update bug reports

10 files changed, 96 insertions, 27 deletions

diff --git a/bugs/icarus_10.md b/bugs/icarus_10.md
index ea9959d..57a954e 100644
--- a/bugs/icarus_10.md
+++ b/bugs/icarus_10.md
@@ -1,6 +1,13 @@
 # Expression evaluates to 1'bx instead of expected 1'b0
 
-[ [Issue 283](https://github.com/steveicarus/iverilog/issues/283) ]
+[ Not fixed | [Issue 283](https://github.com/steveicarus/iverilog/issues/283) ]
+
+## Affected versions
+
+- Icarus Verilog 10.0
+- Icarus Verilog 10.3
+
+## Description
 
 The following code outputs and assigns `y` to 1'bx instead of 1'b0. This happens in iverilog version 10.3 and also happens in version 10.0 (11/23/14) on edaplayground. However, this seems to execute fine in version 9.6 and 9.7 on edaplayground.
 
@@ -35,4 +42,3 @@ iverilog testbench.v -o im && ./im
 the output is `x` instead of `0`.
 
 If the always block is not used, and the expression is assigned to `y` directly, the result is the expected 1'b0. Any changes to the expression seems to fix the result as well.
-
diff --git a/bugs/vivado_1.md b/bugs/vivado_1.md
index ef43cdd..3c94ea6 100644
--- a/bugs/vivado_1.md
+++ b/bugs/vivado_1.md
@@ -1,6 +1,13 @@
 # Verilog If statement nesting crash
 
-[ [Vivado forum 981787](https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Verilog-If-statement-nesting-crash/td-p/981787) ]
+[ Not fixed | [Vivado forum 981787](https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Verilog-If-statement-nesting-crash/td-p/981787) ]
+
+## Affected versions
+
+- Vivado 2019.1
+- Vivado 2018.3
+
+## Description
 
 The following Verilog code crashes on Vivado 2019.1 and 2018.3. it has been reduced as much as possible to a minimal example from a larger design, which produces the crash. Removing any registers or removing the empty if-statements gets rid of the crash.
 
diff --git a/bugs/vivado_2.md b/bugs/vivado_2.md
index c71db3b..40ff962 100644
--- a/bugs/vivado_2.md
+++ b/bugs/vivado_2.md
@@ -1,6 +1,13 @@
 # Vivado 2018.3 synthesis crash
 
-[ [Vivado forum 981136](https://forums.xilinx.com/t5/Synthesis/Vivado-2018-3-synthesis-crash/td-p/981136) ]
+[ Not fixed | [Vivado forum 981136](https://forums.xilinx.com/t5/Synthesis/Vivado-2018-3-synthesis-crash/td-p/981136) ]
+
+## Affected versions
+
+- Vivado 2019.1
+- Vivado 2018.3
+
+## Description
 
 Vivado 2018.3 crashes with the following Verilog code.
 
diff --git a/bugs/vivado_3.md b/bugs/vivado_3.md
index 79fedd5..7bab2e7 100644
--- a/bugs/vivado_3.md
+++ b/bugs/vivado_3.md
@@ -1,6 +1,14 @@
 # Unsigned bit extension in if statement
 
-[ [Vivado forum 981789](https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Unsigned-bit-extension-in-if-statement/td-p/981789) ]
+[ Not fixed | [Vivado forum 981789](https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Unsigned-bit-extension-in-if-statement/td-p/981789) ]
+
+## Affected versions
+
+- Vivado 2019.1
+- Vivado 2018.3
+- Vivado 2018.2
+
+## Description
 
 The code below does not seem to behave properly after synthesis with Vivado 2019.1. When the input to the module is `w1 = 2'b01`, then the output should be 0. This is because the unsigned literal `-1'b1` in the if statement is zero extended to 2 bits giving `-2'b01 = 2'b11`.
 
@@ -10,7 +18,7 @@ However, instead of 0, after synthesis with Vivado, the output it 1. This seems
 
 Assigning `r1` directly to `{-1'b1 == w1}` also works as expected.
 
-```
+```verilog
 module top (y, clk, w1);
    output   y;
    input    clk;
diff --git a/bugs/vivado_4.md b/bugs/vivado_4.md
index 0e7ab04..be3d8a6 100644
--- a/bugs/vivado_4.md
+++ b/bugs/vivado_4.md
@@ -1,10 +1,17 @@
 # Signed with shift in condition synthesis mistmatch
 
-[ [Vivado forum 982518](https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Signed-with-shift-in-condition-synthesis-mistmatch/td-p/982518) ]
+[ Not fixed | [Vivado forum 982518](https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Signed-with-shift-in-condition-synthesis-mistmatch/td-p/982518) ]
 
-The following code seems to give a mismatch after synthesis. I am using Vivado 2019.1 on my personal Arch Linux machineg and Vivado 2018.2 on CentOS 6.
+## Affected versions
 
-```
+- Vivado 2019.1
+- Vivado 2018.2
+
+## Description
+
+The following code seems to give a mismatch after synthesis. I am using Vivado 2019.1 on my personal Arch Linux machine and Vivado 2018.2 on CentOS 6.
+
+```verilog
 module top  (y, w0);
    output [1:0] y;
    input        w0;
diff --git a/bugs/vivado_5.md b/bugs/vivado_5.md
index d34e311..0a971e4 100644
--- a/bugs/vivado_5.md
+++ b/bugs/vivado_5.md
@@ -1,12 +1,22 @@
 # Bit selection synthesis mismatch
 
-[ [Vivado forum 982419](https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Bit-selection-synthesis-mismatch/td-p/982419) ]
+[ Not fixed | [Vivado forum 982419](https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Bit-selection-synthesis-mismatch/td-p/982419) ]
+
+## Affected versions
+
+- Vivado 2019.1
+- Vivado 2018.2
+- Vivado 2017.4
+- Vivado 2016.2
+- Vivado 2016.1
+
+## Description
 
 There seems to be a mismatch between the synthesised net list and the initial design with the following Verilog code. This happens with Vivado 2019.1 on my personal arch linux machine and Vivado 2018.2 on CentoOS 6. I have attached all the necessary files to run it and hopefully reproduce it, together with a testbench that dumps a vcd file.
 
 I have reduced the Verilog as much as possible, and changing anything else makes Vivado synthesise correctly.
 
-```
+```verilog
 module top (y, clk, w0);
    output [1:0] y;
    input clk;
diff --git a/bugs/yosys_6.md b/bugs/yosys_6.md
index 619bb04..eb487fd 100644
--- a/bugs/yosys_6.md
+++ b/bugs/yosys_6.md
@@ -1,6 +1,12 @@
 # Yosys aborts with exception in peephole optimizers pass
 
-[ [Issue 993](https://github.com/YosysHQ/yosys/issues/993) ]
+[ Fixed in [`b37c31e`](https://github.com/YosysHQ/yosys/commit/b37c31e2cb82343e363d39e4b35ebdb82f4f69a3) | [Issue 993](https://github.com/YosysHQ/yosys/issues/993) ]
+
+## Affected versions
+
+- Yosys 0.8+411
+
+## Description
 
 Yosys aborts with a `vector::_M_range_check` exception in the peephole optimizers pass (`PEEPOPT pass`). This happens with the verilog code below, which I have reduced as much as possible into an MCVE.
 
@@ -21,7 +27,7 @@ module top(y, clk, wire1);
 endmodule
 ```
 
-## Steps to reproduce the issue
+### Steps to reproduce the issue
 
 Yosys version that this was tested with: `Yosys 0.8+411 (git sha1 70d0f389, clang 8.0.0 -fPIC -Os)`, which is the current master.
 
@@ -31,7 +37,7 @@ The following command was used to synthesise the design:
 yosys -p 'read -formal rtl.v; synth; write_verilog rtl_yosys.v'
 ```
 
-## Expected behavior
+### Expected behavior
 
 Synthesis without any exceptions.
 
@@ -56,7 +62,7 @@ found and reported 0 problems.
 Dumping module `\top'.
 ```
 
-## Actual behavior
+### Actual behavior
 
 Yosys aborts with a `vector::_M_range_check` exception.
 
diff --git a/bugs/yosys_7.md b/bugs/yosys_7.md
index c37d9b5..9e35436 100644
--- a/bugs/yosys_7.md
+++ b/bugs/yosys_7.md
@@ -1,8 +1,14 @@
 # Initial value of register ignored during synthesis
 
-[ [Issue 997](https://github.com/YosysHQ/yosys/issues/997) ]
+[ Fixed in [`33738c1`](https://github.com/YosysHQ/yosys/commit/33738c174560c718723b6c860af002d1a8a91cea) | [Issue 997](https://github.com/YosysHQ/yosys/issues/997) ]
 
-## Steps to reproduce the issue
+## Affected versions
+
+- Yosys 0.8+450
+
+## Description 
+
+### Steps to reproduce the issue
 
 Consider the following verilog code.
 
@@ -35,7 +41,7 @@ the initial value of the register seems to be ignored. Therefore, during simulat
 
 This does not seem to happen with the official 0.8 release of Yosys. In that release, the expected behavior is generated.
 
-## Expected behavior
+### Expected behavior
 
 It is expected that the register is initialised with 0. This was generated using the 0.8 release of Yosys.
 
@@ -56,7 +62,7 @@ module top_1(y, clk, wire4);
 endmodule
 ```
 
-## Actual behavior
+### Actual behavior
 
 However, it actually gets initialised with `1'hx`.
 
diff --git a/bugs/yosys_8.md b/bugs/yosys_8.md
index 9840f34..56d5e49 100644
--- a/bugs/yosys_8.md
+++ b/bugs/yosys_8.md
@@ -1,8 +1,14 @@
 # Synthesis issue with shift and multiplication
 
-[ [Issue 1047](https://github.com/YosysHQ/yosys/issues/1047) ]
+[ Fixed in [`349c472`](https://github.com/YosysHQ/yosys/commit/349c47250a9779bc58634870d2e3facfe95fbff8) | [Issue 1047](https://github.com/YosysHQ/yosys/issues/1047) ]
 
-## Steps to reproduce the issue
+## Affected versions
+
+- Yosys 0.8+498
+
+## Description
+
+### Steps to reproduce the issue
 
 Consider the following Verilog code
 
@@ -26,11 +32,11 @@ and the following command
 yosys -p 'read -formal rtl.v; synth; write_verilog -noattr syn_yosys.v'
 ```
 
-## Expected behavior
+### Expected behavior
 
 When passing the input `3'b100`, I would expect the output to give `1'b1`, as `3'b100 * 3'b110 = 3'b000`.
 
-## Actual behavior
+### Actual behavior
 
 The synthesised output is the following, which when given `3'b100` gives `1'b0` as output.
 
diff --git a/bugs/yosys_9.md b/bugs/yosys_9.md
index cafdf86..4e92ce7 100644
--- a/bugs/yosys_9.md
+++ b/bugs/yosys_9.md
@@ -1,8 +1,14 @@
 # Unexpected behaviour of for loop and if statement
 
-[ [Issue 1243](https://github.com/YosysHQ/yosys/issues/1243) ]
+[ Fixed in [`39f4c10`](https://github.com/YosysHQ/yosys/commit/39f4c1096ac3b5964bfa087c2b7f2e8d5a9c1ef3) | [Issue 1243](https://github.com/YosysHQ/yosys/issues/1243) ]
 
-## Steps to reproduce the issue
+## Affected versions
+
+- Yosys 0.8+618
+
+## Description
+
+### Steps to reproduce the issue
 
 Consider the following piece of code:
 
@@ -41,7 +47,7 @@ yosys -p "read_verilog rtl.v; synth; write_verilog -noattr synth.v"
 
 I have also attached a folder containing a test bench and SymbiYosys script to compare the design to the synthesised net list.
 
-## Expected behaviour
+### Expected behaviour
 
 I would expect this to be implemented by assigning `sel` to `y`. This is actually also the output of a previous version of Yosys (`Yosys 0.8+508 (git sha1 c2ea3746, clang 8.0.0 -fPIC -Os)`)
 
@@ -58,7 +64,7 @@ module top(y, clk, sel);
 endmodule
 ```
 
-## Actual behaviour
+### Actual behaviour
 
 However, with Yosys, `y` is set to a constant 0.