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| author | Yann Herklotz <git@ymhg.org> | 2019-04-06 21:57:13 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-06 21:57:13 +0100 |
| commit | 9aced8f8ea480a6aa29acd470857677074bdfd97 (patch) | |
| tree | c2f11462b77e5d2497ace8d193a22f80ef568a24 /data/cells_yosys.v | |
| parent | 03c1311b2f3dc4be7909464d21cb42c1c8400001 (diff) | |
| download | verismith-9aced8f8ea480a6aa29acd470857677074bdfd97.tar.gz verismith-9aced8f8ea480a6aa29acd470857677074bdfd97.zip | |
Add more primitives to data/
Diffstat (limited to 'data/cells_yosys.v')
| -rw-r--r-- | data/cells_yosys.v | 20 |
1 files changed, 13 insertions, 7 deletions
diff --git a/data/cells_yosys.v b/data/cells_yosys.v index 48f9c66..adb8adb 100644 --- a/data/cells_yosys.v +++ b/data/cells_yosys.v @@ -1,13 +1,19 @@ -// Taken from yosys verilog files. +// Taken from yosys simcells.v module \$_DLATCH_N_ (E, D, Q); - wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; - input E, D; - output Q = !E ? D : Q; + input E, D; + output reg Q; + always @* begin + if (E == 0) + Q <= D; + end endmodule module \$_DLATCH_P_ (E, D, Q); - wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; - input E, D; - output Q = E ? D : Q; + input E, D; + output reg Q; + always @* begin + if (E == 1) + Q <= D; + end endmodule |