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author | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-27 14:40:54 +0100 |
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committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-27 14:40:54 +0100 |
commit | c3c561e529b31d6a146621ad7ca2826327a8e87c (patch) | |
tree | dccfd6284deb93bc5c0d7cad5f59116424c1489d /examples | |
parent | 0bbae2481444d02413df374ddde1a9bd8342b24a (diff) | |
download | verismith-c3c561e529b31d6a146621ad7ca2826327a8e87c.tar.gz verismith-c3c561e529b31d6a146621ad7ca2826327a8e87c.zip |
Add another example for declarations in verilog
Diffstat (limited to 'examples')
-rw-r--r-- | examples/decl.v | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/examples/decl.v b/examples/decl.v new file mode 100644 index 0000000..8f27245 --- /dev/null +++ b/examples/decl.v @@ -0,0 +1,31 @@ +module and_comb(clk, out, in1, in2); + input wire [7:0] in1; + input wire [7:0] in2; + input wire clk; + output reg [7:0] out; + + always @(posedge clk) + begin + out <= in1 & in2; + end +endmodule + +module main; + wire [7:0] c; + reg [7:0] a; + reg [7:0] b; + reg clk; + + and_comb gate(.in1(a), .in2(b), .out(c), .clk(clk)); + + initial + begin + a = 8'd29; + b = 8'd95; + clk = 1'b0; + #10; + clk = 1'b1; + #10 $display("%d & %d = %d", a, b, c); + $finish; + end +endmodule |