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| author | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-29 23:42:18 +0100 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-29 23:42:18 +0100 |
| commit | 40b09529403cf7b7190a45596d36c2f200504988 (patch) | |
| tree | 9199615ce797d64650a9f4cf8a555a8f6b73c62b /src/Test/VeriFuzz/Graph/ASTGen.hs | |
| parent | 97462372591b8bae4eb34a35197c2b606c0c8bd7 (diff) | |
| download | verismith-40b09529403cf7b7190a45596d36c2f200504988.tar.gz verismith-40b09529403cf7b7190a45596d36c2f200504988.zip | |
Add remove duplicates
Diffstat (limited to 'src/Test/VeriFuzz/Graph/ASTGen.hs')
| -rw-r--r-- | src/Test/VeriFuzz/Graph/ASTGen.hs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/Test/VeriFuzz/Graph/ASTGen.hs b/src/Test/VeriFuzz/Graph/ASTGen.hs index 28dc32a..00eb71d 100644 --- a/src/Test/VeriFuzz/Graph/ASTGen.hs +++ b/src/Test/VeriFuzz/Graph/ASTGen.hs @@ -73,11 +73,11 @@ genAssignAST c = catMaybes $ genContAssignAST c <$> nodes nodes = G.labNodes gr genModuleDeclAST :: Circuit -> ModDecl -genModuleDeclAST c = ModDecl id Nothing ports items +genModuleDeclAST c = ModDecl id output ports items where id = Identifier "gen_module" ports = genPortsAST inputsC c - outPut = safe head $ genPortsAST inputsC c + output = Just $ Port (PortNet Wire) "y" items = genAssignAST c generateAST :: Circuit -> VerilogSrc |