| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Rename files out of the module | Yann Herklotz | 2019-01-10 | 1 | -86/+0 |
| * | Rename module names so that I can move them | Yann Herklotz | 2019-01-10 | 1 | -12/+12 |
| * | Make generated wires longer | Yann Herklotz | 2019-01-09 | 1 | -3/+5 |
| * | Fix linting warnings | Yann Herklotz | 2019-01-01 | 1 | -2/+2 |
| * | Large refactor | Yann Herklotz | 2018-12-31 | 1 | -6/+6 |
| * | [Fix #13, Fix #15] Fix type errors and add inst functions | Yann Herklotz | 2018-12-30 | 1 | -1/+1 |
| * | [Fix #14] Add size to Port type | Yann Herklotz | 2018-12-30 | 1 | -2/+2 |
| * | Add remove duplicates | Yann Herklotz | 2018-12-29 | 1 | -2/+2 |
| * | Changes to the API | Yann Herklotz | 2018-12-29 | 1 | -14/+21 |
| * | Fix documentation and copyright | Yann Herklotz | 2018-12-28 | 1 | -3/+3 |
| * | Fix imports and cabal file | Yann Herklotz | 2018-12-28 | 1 | -3/+3 |
| * | Remove OverloadedStrings in favour of declaration in module | Yann Herklotz | 2018-12-27 | 1 | -2/+0 |
| * | Type fixes | Yann Herklotz | 2018-12-25 | 1 | -7/+8 |
| * | Format ASTGen | Yann Herklotz | 2018-12-22 | 1 | -6/+3 |
| * | [Fix #2] Add generation of AST from Circuit | Yann Herklotz | 2018-12-22 | 1 | -8/+21 |
| * | Add more functions to the code generation | Yann Herklotz | 2018-12-22 | 1 | -15/+18 |
| * | Add more AST generation | Yann Herklotz | 2018-12-20 | 1 | -1/+19 |
| * | Add AST generation | Yann Herklotz | 2018-12-15 | 1 | -0/+47 |
 |
index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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