Add simulator module

1 files changed, 48 insertions, 0 deletions

diff --git a/src/Test/VeriFuzz/Simulator/General.hs b/src/Test/VeriFuzz/Simulator/General.hs
new file mode 100644
index 0000000..e5307ea
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+++ b/src/Test/VeriFuzz/Simulator/General.hs
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+{-|
+Module      : Test.VeriFuzz.Simulator.General
+Description : Class of the simulator.
+Copyright   : (c) Yann Herklotz Grave 2018
+License     : GPL-3
+Maintainer  : ymherklotz@gmail.com
+Stability   : experimental
+Portability : POSIX
+
+Class of the simulator and the synthesize tool.
+-}
+
+module Test.VeriFuzz.Simulator.General where
+
+import           Data.Text                 (Text)
+import           Prelude                   hiding (FilePath)
+import           Shelly
+import           Test.VeriFuzz.Verilog.AST
+
+-- | Simulator class.
+class Simulator a where
+  toText :: a -> Text
+
+-- | Simulation type class.
+class (Simulator a) => Simulate a where
+  runSim :: a       -- ^ Simulator instance
+         -> ModDecl -- ^ Module to simulate
+         -> [Int]   -- ^ Inputs to simulate
+         -> Sh Int  -- ^ Returns the value of the hash at the output of the testbench
+
+-- | Synthesize type class.
+class (Simulator a) => Synthesize a where
+  runSynth :: a        -- ^ Synthesize tool instance
+           -> ModDecl  -- ^ Module to synthesize
+           -> FilePath -- ^ Output verilog file for the module
+           -> Sh ()    -- ^ does not return any values
+
+timeout :: Text -> [Text] -> Sh Text
+timeout = command1 "timeout" ["180"]
+
+timeout_ :: Text -> [Text] -> Sh ()
+timeout_ = command1_ "timeout" ["180"]
+
+synthesizers :: [Text]
+synthesizers = ["yosys", "xst"]
+
+simulators :: [Text]
+simulators = ["yosim", "iverilog"]