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| author | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-30 19:44:40 +0100 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-30 19:44:40 +0100 |
| commit | cabb2cec0bde620c49b1d7a36cd8226f579c1023 (patch) | |
| tree | a3f0cfcd487f5c58179706d75f5ef70917c9a760 /src/Test/VeriFuzz/Verilog/Helpers.hs | |
| parent | 9f2bb8aff3198d36ac847dde67e4e630cd8b889f (diff) | |
| download | verismith-cabb2cec0bde620c49b1d7a36cd8226f579c1023.tar.gz verismith-cabb2cec0bde620c49b1d7a36cd8226f579c1023.zip | |
[Fix #13, Fix #15] Fix type errors and add inst functions
Diffstat (limited to 'src/Test/VeriFuzz/Verilog/Helpers.hs')
| -rw-r--r-- | src/Test/VeriFuzz/Verilog/Helpers.hs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/Test/VeriFuzz/Verilog/Helpers.hs b/src/Test/VeriFuzz/Verilog/Helpers.hs index 4410532..6712d32 100644 --- a/src/Test/VeriFuzz/Verilog/Helpers.hs +++ b/src/Test/VeriFuzz/Verilog/Helpers.hs @@ -32,7 +32,7 @@ numExpr = ((PrimExpr . PrimNum) .) . Number -- | Create an empty module. emptyMod :: ModDecl -emptyMod = ModDecl "" Nothing [] [] +emptyMod = ModDecl "" [] [] [] -- | Set a module name for a module declaration. setModName :: Text -> ModDecl -> ModDecl @@ -47,7 +47,7 @@ addDescription desc = getVerilogSrc %~ (:) desc testBench :: ModDecl testBench = - ModDecl "main" Nothing [] + ModDecl "main" [] [] [ regDecl "a" , regDecl "b" , wireDecl "c" |