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| author | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-31 19:13:25 +0100 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-31 19:13:25 +0100 |
| commit | de580a7d4b5f4def9f0b71c6cff33ccad45d678b (patch) | |
| tree | d7632f745db918da754b21ed951e30351a459f41 /src/Test/VeriFuzz/Verilog/Helpers.hs | |
| parent | b679d2c6b19f647a3af98019426dfd05e8e103e9 (diff) | |
| download | verismith-de580a7d4b5f4def9f0b71c6cff33ccad45d678b.tar.gz verismith-de580a7d4b5f4def9f0b71c6cff33ccad45d678b.zip | |
Large refactor
Diffstat (limited to 'src/Test/VeriFuzz/Verilog/Helpers.hs')
| -rw-r--r-- | src/Test/VeriFuzz/Verilog/Helpers.hs | 18 |
1 files changed, 7 insertions, 11 deletions
diff --git a/src/Test/VeriFuzz/Verilog/Helpers.hs b/src/Test/VeriFuzz/Verilog/Helpers.hs index d3bc689..b04aa76 100644 --- a/src/Test/VeriFuzz/Verilog/Helpers.hs +++ b/src/Test/VeriFuzz/Verilog/Helpers.hs @@ -21,14 +21,10 @@ regDecl :: Identifier -> ModItem regDecl = Decl Nothing . Port (Reg False) 1 wireDecl :: Identifier -> ModItem -wireDecl = Decl Nothing . Port (PortNet Wire) 1 +wireDecl = Decl Nothing . Port Wire 1 -modConn :: Text -> ModConn -modConn = ModConn . PrimExpr . PrimId . Identifier - --- | Create a number expression which will be stored in a primary expression. -numExpr :: Int -> Int -> Expression -numExpr = ((PrimExpr . PrimNum) .) . Number +modConn :: Identifier -> ModConn +modConn = ModConn . Id -- | Create an empty module. emptyMod :: ModDecl @@ -57,10 +53,10 @@ testBench = , modConn "b" ] , Initial $ SeqBlock - [ BlockAssign . Assign (RegId "a") Nothing . PrimExpr . PrimNum $ Number 1 1 - , BlockAssign . Assign (RegId "b") Nothing . PrimExpr . PrimNum $ Number 1 1 + [ BlockAssign . Assign (RegId "a") Nothing $ Number 1 1 + , BlockAssign . Assign (RegId "b") Nothing $ Number 1 1 -- , TimeCtrl (Delay 1) . Just . SysTaskEnable $ Task "display" - -- [ ExprStr "%d & %d = %d" + -- [ Str "%d & %d = %d" -- , PrimExpr $ PrimId "a" -- , PrimExpr $ PrimId "b" -- , PrimExpr $ PrimId "c" @@ -73,4 +69,4 @@ addTestBench :: VerilogSrc -> VerilogSrc addTestBench = addDescription $ Description testBench defaultPort :: Identifier -> Port -defaultPort = Port (PortNet Wire) 1 +defaultPort = Port Wire 1 |