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author | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-10 15:49:13 +0000 |
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committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-10 15:49:13 +0000 |
commit | dac34f6ff5c46f11fe6c548b92a02ebf4f10d7e9 (patch) | |
tree | e51f51b4e82f3c764bcba88725e20e4fb10284da /src/Test/VeriFuzz/Verilog/Helpers.hs | |
parent | 3f1190cd7fc873449a1fd430386aa4b773d010ac (diff) | |
download | verismith-dac34f6ff5c46f11fe6c548b92a02ebf4f10d7e9.tar.gz verismith-dac34f6ff5c46f11fe6c548b92a02ebf4f10d7e9.zip |
Rename files out of the module
Diffstat (limited to 'src/Test/VeriFuzz/Verilog/Helpers.hs')
-rw-r--r-- | src/Test/VeriFuzz/Verilog/Helpers.hs | 75 |
1 files changed, 0 insertions, 75 deletions
diff --git a/src/Test/VeriFuzz/Verilog/Helpers.hs b/src/Test/VeriFuzz/Verilog/Helpers.hs deleted file mode 100644 index 0204379..0000000 --- a/src/Test/VeriFuzz/Verilog/Helpers.hs +++ /dev/null @@ -1,75 +0,0 @@ -{-| -Module : VeriFuzz.Verilog.Helpers -Description : Defaults and common functions. -Copyright : (c) 2018-2019, Yann Herklotz Grave -License : BSD-3 -Maintainer : ymherklotz [at] gmail [dot] com -Stability : experimental -Portability : POSIX - -Defaults and common functions. --} - -module VeriFuzz.Verilog.Helpers where - -import Control.Lens -import Data.Text (Text) -import qualified Data.Text -import VeriFuzz.Verilog.AST - -regDecl :: Identifier -> ModItem -regDecl = Decl Nothing . Port (Reg False) 1 - -wireDecl :: Identifier -> ModItem -wireDecl = Decl Nothing . Port Wire 1 - -modConn :: Identifier -> ModConn -modConn = ModConn . Id - --- | Create an empty module. -emptyMod :: ModDecl -emptyMod = ModDecl "" [] [] [] - --- | Set a module name for a module declaration. -setModName :: Text -> ModDecl -> ModDecl -setModName str = moduleId .~ Identifier str - --- | Add a input port to the module declaration. -addModPort :: Port -> ModDecl -> ModDecl -addModPort port = modInPorts %~ (:) port - -addDescription :: Description -> VerilogSrc -> VerilogSrc -addDescription desc = getVerilogSrc %~ (:) desc - -testBench :: ModDecl -testBench = - ModDecl "main" [] [] - [ regDecl "a" - , regDecl "b" - , wireDecl "c" - , ModInst "and" "and_gate" - [ modConn "c" - , modConn "a" - , modConn "b" - ] - , Initial $ SeqBlock - [ BlockAssign . Assign (RegId "a") Nothing $ Number 1 1 - , BlockAssign . Assign (RegId "b") Nothing $ Number 1 1 - -- , TimeCtrl (Delay 1) . Just . SysTaskEnable $ Task "display" - -- [ Str "%d & %d = %d" - -- , PrimExpr $ PrimId "a" - -- , PrimExpr $ PrimId "b" - -- , PrimExpr $ PrimId "c" - -- ] - -- , SysTaskEnable $ Task "finish" [] - ] - ] - -addTestBench :: VerilogSrc -> VerilogSrc -addTestBench = addDescription $ Description testBench - -defaultPort :: Identifier -> Port -defaultPort = Port Wire 1 - -portToExpr :: Port -> Expr -portToExpr (Port _ _ id) = Id id |