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authorYann Herklotz <ymherklotz@gmail.com>2019-01-10 15:48:13 +0000
committerYann Herklotz <ymherklotz@gmail.com>2019-01-10 15:48:21 +0000
commit3f1190cd7fc873449a1fd430386aa4b773d010ac (patch)
treeba9efed7478213d56c5b2ee5699225d684824373 /src/Test/VeriFuzz/Verilog/Mutate.hs
parent9f829c41651cd2872b1c6e666b5bceeebf829aee (diff)
downloadverismith-3f1190cd7fc873449a1fd430386aa4b773d010ac.tar.gz
verismith-3f1190cd7fc873449a1fd430386aa4b773d010ac.zip
Rename module names so that I can move them
Diffstat (limited to 'src/Test/VeriFuzz/Verilog/Mutate.hs')
-rw-r--r--src/Test/VeriFuzz/Verilog/Mutate.hs16
1 files changed, 8 insertions, 8 deletions
diff --git a/src/Test/VeriFuzz/Verilog/Mutate.hs b/src/Test/VeriFuzz/Verilog/Mutate.hs
index 367516a..501d217 100644
--- a/src/Test/VeriFuzz/Verilog/Mutate.hs
+++ b/src/Test/VeriFuzz/Verilog/Mutate.hs
@@ -1,5 +1,5 @@
{-|
-Module : Test.VeriFuzz.Verilog.Mutation
+Module : VeriFuzz.Verilog.Mutation
Description : Functions to mutate the Verilog AST.
Copyright : (c) 2018-2019, Yann Herklotz Grave
License : BSD-3
@@ -7,18 +7,18 @@ Maintainer : ymherklotz [at] gmail [dot] com
Stability : experimental
Portability : POSIX
-Functions to mutate the Verilog AST from "Test.VeriFuzz.Verilog.AST" to generate
+Functions to mutate the Verilog AST from "VeriFuzz.Verilog.AST" to generate
more random patterns, such as nesting wires instead of creating new ones.
-}
-module Test.VeriFuzz.Verilog.Mutate where
+module VeriFuzz.Verilog.Mutate where
import Control.Lens
-import Data.Maybe (catMaybes, fromMaybe)
-import Test.VeriFuzz.Internal.Gen
-import Test.VeriFuzz.Internal.Shared
-import Test.VeriFuzz.Verilog.AST
-import Test.VeriFuzz.Verilog.CodeGen
+import Data.Maybe (catMaybes, fromMaybe)
+import VeriFuzz.Internal.Gen
+import VeriFuzz.Internal.Shared
+import VeriFuzz.Verilog.AST
+import VeriFuzz.Verilog.CodeGen
-- | Return if the 'Identifier' is in a 'ModDecl'.
inPort :: Identifier -> ModDecl -> Bool