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| author | Yann Herklotz <git@ymhg.org> | 2019-04-03 19:53:56 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-03 19:53:56 +0100 |
| commit | 31325e890e8a7807ec5a3d996c3789baad0e8dc4 (patch) | |
| tree | c3df20e33ff945c1ec10fc132ff7a12127176703 /src/VeriFuzz.hs | |
| parent | 6776d38b11186e97101995eb2c071096cc1d648b (diff) | |
| download | verismith-31325e890e8a7807ec5a3d996c3789baad0e8dc4.tar.gz verismith-31325e890e8a7807ec5a3d996c3789baad0e8dc4.zip | |
Generate Verilog instead of ModDecl
Diffstat (limited to 'src/VeriFuzz.hs')
| -rw-r--r-- | src/VeriFuzz.hs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/VeriFuzz.hs b/src/VeriFuzz.hs index e008d62..b6b134b 100644 --- a/src/VeriFuzz.hs +++ b/src/VeriFuzz.hs @@ -113,10 +113,10 @@ checkEquivalence src dir = shellyFailDir $ do -- | Run a fuzz run and check if all of the simulators passed by checking if the -- generated Verilog files are equivalent. -runEquivalence :: Gen ModDecl -> Text -> Int -> IO () +runEquivalence :: Gen Verilog -> Text -> Int -> IO () runEquivalence gm t i = do m <- Hog.sample gm - let srcInfo = makeSrcInfo m + let srcInfo = SourceInfo "top" m rand <- generateByteString 20 shellyFailDir $ do mkdir_p (fromText "output" </> fromText n) |