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authorYann Herklotz Grave <git@yannherklotzgrave.com>2019-02-16 20:19:00 +0000
committerYann Herklotz Grave <git@yannherklotzgrave.com>2019-02-16 20:19:00 +0000
commit5025a43948a682bc40d5c91606ec97cd8d6c3897 (patch)
treeb31c5113ff0a7d93424ba21a6c288f704f24dc78 /src/VeriFuzz/AST.hs
parenta180c89947f8e0c191ba7e7dba4c6eb7edf538e6 (diff)
downloadverismith-5025a43948a682bc40d5c91606ec97cd8d6c3897.tar.gz
verismith-5025a43948a682bc40d5c91606ec97cd8d6c3897.zip
Change Port type, adding signed info
Diffstat (limited to 'src/VeriFuzz/AST.hs')
-rw-r--r--src/VeriFuzz/AST.hs22
1 files changed, 11 insertions, 11 deletions
diff --git a/src/VeriFuzz/AST.hs b/src/VeriFuzz/AST.hs
index f5d1824..34d9327 100644
--- a/src/VeriFuzz/AST.hs
+++ b/src/VeriFuzz/AST.hs
@@ -47,9 +47,9 @@ module VeriFuzz.AST
-- ** Ports
, PortDir(..)
, PortType(..)
- , regSigned
, Port(..)
, portType
+ , portSigned
, portSize
, portName
-- * Expression
@@ -411,11 +411,11 @@ instance QC.Arbitrary PortDir where
-- | Currently, only @wire@ and @reg@ are supported, as the other net types are
-- not that common and not a priority.
data PortType = Wire
- | Reg { _regSigned :: Bool }
+ | Reg
deriving (Eq, Show, Data)
instance QC.Arbitrary PortType where
- arbitrary = QC.oneof [pure Wire, Reg <$> QC.arbitrary]
+ arbitrary = QC.elements [Wire, Reg]
makeLenses ''PortType
@@ -427,15 +427,17 @@ makeLenses ''PortType
--
-- This is now implemented inside 'ModDecl' itself, which uses a list of output
-- and input ports.
-data Port = Port { _portType :: PortType
- , _portSize :: Int
- , _portName :: Identifier
+data Port = Port { _portType :: PortType
+ , _portSigned :: Bool
+ , _portSize :: Int
+ , _portName :: Identifier
} deriving (Eq, Show, Data)
makeLenses ''Port
instance QC.Arbitrary Port where
- arbitrary = Port <$> QC.arbitrary <*> positiveArb <*> QC.arbitrary
+ arbitrary = Port <$> QC.arbitrary <*> QC.arbitrary
+ <*> positiveArb <*> QC.arbitrary
-- | This is currently a type because direct module declaration should also be
-- added:
@@ -565,10 +567,8 @@ traverseModItem _ e = pure e
makeLenses ''ModDecl
modPortGen :: QC.Gen Port
-modPortGen = QC.oneof
- [ Port Wire <$> positiveArb <*> QC.arbitrary
- , Port <$> (Reg <$> QC.arbitrary) <*> positiveArb <*> QC.arbitrary
- ]
+modPortGen = Port <$> QC.arbitrary <*> QC.arbitrary
+ <*> QC.arbitrary <*> QC.arbitrary
instance QC.Arbitrary ModDecl where
arbitrary = ModDecl <$> QC.arbitrary <*> QC.arbitrary <*> QC.listOf1 modPortGen <*> QC.arbitrary