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| author | Yann Herklotz <git@ymhg.org> | 2019-04-02 18:16:21 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-02 18:16:21 +0100 |
| commit | c0c799ab3f79c370e4c33b8f824489ce8b1c96ec (patch) | |
| tree | 042f235cdf458e6bf5330a477435d4b34bee7859 /src/VeriFuzz/ASTGen.hs | |
| parent | 1ef0455ddad821c2ddf64d451e99b8b5508c39c5 (diff) | |
| download | verismith-c0c799ab3f79c370e4c33b8f824489ce8b1c96ec.tar.gz verismith-c0c799ab3f79c370e4c33b8f824489ce8b1c96ec.zip | |
Rename to Verilog
Diffstat (limited to 'src/VeriFuzz/ASTGen.hs')
| -rw-r--r-- | src/VeriFuzz/ASTGen.hs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/VeriFuzz/ASTGen.hs b/src/VeriFuzz/ASTGen.hs index 7c295e1..9360a88 100644 --- a/src/VeriFuzz/ASTGen.hs +++ b/src/VeriFuzz/ASTGen.hs @@ -75,5 +75,5 @@ genModuleDeclAST c = ModDecl i output ports $ combineAssigns yPort a a = genAssignAST c yPort = Port Wire False 90 "y" -generateAST :: Circuit -> VerilogSrc -generateAST c = VerilogSrc [Description $ genModuleDeclAST c] +generateAST :: Circuit -> Verilog +generateAST c = Verilog [Description $ genModuleDeclAST c] |