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| author | Yann Herklotz <git@ymhg.org> | 2019-04-02 18:16:21 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-02 18:16:21 +0100 |
| commit | c0c799ab3f79c370e4c33b8f824489ce8b1c96ec (patch) | |
| tree | 042f235cdf458e6bf5330a477435d4b34bee7859 /src/VeriFuzz/Gen.hs | |
| parent | 1ef0455ddad821c2ddf64d451e99b8b5508c39c5 (diff) | |
| download | verismith-c0c799ab3f79c370e4c33b8f824489ce8b1c96ec.tar.gz verismith-c0c799ab3f79c370e4c33b8f824489ce8b1c96ec.zip | |
Rename to Verilog
Diffstat (limited to 'src/VeriFuzz/Gen.hs')
| -rw-r--r-- | src/VeriFuzz/Gen.hs | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/VeriFuzz/Gen.hs b/src/VeriFuzz/Gen.hs index b9545a8..6bc01c9 100644 --- a/src/VeriFuzz/Gen.hs +++ b/src/VeriFuzz/Gen.hs @@ -75,7 +75,7 @@ fromGraph = do $ initMod . head $ nestUpTo 5 (generateAST gr) - ^.. getVerilogSrc + ^.. getVerilog . traverse . getDescription @@ -206,8 +206,8 @@ moduleDef top = do -- | Procedural generation method for random Verilog. Uses internal 'Reader' and -- 'State' to keep track of the current Verilog code structure. -procedural :: Config -> Gen VerilogSrc -procedural config = VerilogSrc . (: []) . Description <$> Hog.resize +procedural :: Config -> Gen Verilog +procedural config = Verilog . (: []) . Description <$> Hog.resize num (runReaderT (evalStateT (moduleDef True) context) config) where |