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authorYann Herklotz Grave <git@yannherklotzgrave.com>2019-03-01 19:18:05 +0000
committerYann Herklotz Grave <git@yannherklotzgrave.com>2019-03-01 19:18:05 +0000
commitad199f8087642573f4f7daeeb588a43faaa3eab3 (patch)
tree067e3ee13861e2ed8141e196a9fe9d96b3191b0b /src/VeriFuzz/Internal/Simulator.hs
parentdba53cd980a215936cffaedb84ad1e4c0784beee (diff)
downloadverismith-ad199f8087642573f4f7daeeb588a43faaa3eab3.tar.gz
verismith-ad199f8087642573f4f7daeeb588a43faaa3eab3.zip
Add lens to access main module in SourceInfo
Diffstat (limited to 'src/VeriFuzz/Internal/Simulator.hs')
-rw-r--r--src/VeriFuzz/Internal/Simulator.hs17
1 files changed, 13 insertions, 4 deletions
diff --git a/src/VeriFuzz/Internal/Simulator.hs b/src/VeriFuzz/Internal/Simulator.hs
index 5712709..1454a0f 100644
--- a/src/VeriFuzz/Internal/Simulator.hs
+++ b/src/VeriFuzz/Internal/Simulator.hs
@@ -12,7 +12,7 @@ Class of the simulator and the synthesize tool.
module VeriFuzz.Internal.Simulator where
-import Control.Lens ((^.), (^..))
+import Control.Lens
import Data.Bits (shiftL)
import Data.ByteString (ByteString)
import qualified Data.ByteString as B
@@ -48,10 +48,19 @@ class (Tool a) => Synthesisor a where
data SourceInfo = SourceInfo { runMainModule :: {-# UNPACK #-} !Text
, runSource :: !VerilogSrc
}
+ deriving (Eq, Show)
-mainModule :: SourceInfo -> ModDecl
-mainModule (SourceInfo main src) = head . filter ismain $ src ^.. getModule
- where ismain v = v ^. modId . getIdentifier == main
+-- | May need to change this to Traversal to be safe. For now it will fail when
+-- the main has not been properly set with.
+mainModule :: Lens' SourceInfo ModDecl
+mainModule = lens get_ set_
+ where
+ set_ (SourceInfo top main) v =
+ SourceInfo top (main & getModule %~ update top v)
+ update top v m@(ModDecl (Identifier i) _ _ _) | i == top = v
+ | otherwise = m
+ get_ (SourceInfo top main) = head . filter (f top) $ main ^.. getModule
+ f top (ModDecl (Identifier i) _ _ _) = i == top
rootPath :: Sh FilePath
rootPath = do