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| author | Yann Herklotz <git@ymhg.org> | 2019-04-02 18:16:21 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-02 18:16:21 +0100 |
| commit | c0c799ab3f79c370e4c33b8f824489ce8b1c96ec (patch) | |
| tree | 042f235cdf458e6bf5330a477435d4b34bee7859 /src/VeriFuzz/Mutate.hs | |
| parent | 1ef0455ddad821c2ddf64d451e99b8b5508c39c5 (diff) | |
| download | verismith-c0c799ab3f79c370e4c33b8f824489ce8b1c96ec.tar.gz verismith-c0c799ab3f79c370e4c33b8f824489ce8b1c96ec.zip | |
Rename to Verilog
Diffstat (limited to 'src/VeriFuzz/Mutate.hs')
| -rw-r--r-- | src/VeriFuzz/Mutate.hs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/VeriFuzz/Mutate.hs b/src/VeriFuzz/Mutate.hs index 4985993..1984805 100644 --- a/src/VeriFuzz/Mutate.hs +++ b/src/VeriFuzz/Mutate.hs @@ -67,11 +67,11 @@ nestId i m def = Id i -- | Replaces an identifier by a expression in all the module declaration. -nestSource :: Identifier -> VerilogSrc -> VerilogSrc +nestSource :: Identifier -> Verilog -> Verilog nestSource i src = src & getModule %~ nestId i -- | Nest variables in the format @w[0-9]*@ up to a certain number. -nestUpTo :: Int -> VerilogSrc -> VerilogSrc +nestUpTo :: Int -> Verilog -> Verilog nestUpTo i src = foldl (flip nestSource) src $ Identifier . fromNode <$> [1 .. i] |